 | 2011 |
| 20 |  | Nauman H. Khan,
Syed M. Alam,
Soha Hassoun:
Mitigating TSV-induced substrate noise in 3-D ICs using GND plugs.
ISQED 2011: 751-756 |
| 19 |  | Jayita Das,
Syed M. Alam,
Srinath Rajaram,
Sanjukta Bhanja:
Hybrid CMOS-MQCA Logic Architectures using Multi-Layer Spintronic Devices
CoRR abs/1102.4034: (2011) |
| 18 |  | Nauman H. Khan,
Syed M. Alam,
Soha Hassoun:
Power Delivery Design for 3-D ICs Using Different Through-Silicon Via (TSV) Technologies.
IEEE Trans. VLSI Syst. 19(4): 647-658 (2011) |
| 17 |  | Ankur Jain,
Syed M. Alam,
Scott Pozder,
Robert E. Jones:
Thermal-electrical co-optimisation of floorplanning of three-dimensional integrated circuits under manufacturing and physical design constraints.
IET Computers & Digital Techniques 5(3): 169-178 (2011) |
| 16 |  | Karthikeyan Lingasubramanian,
Syed M. Alam,
Sanjukta Bhanja:
Maximum error modeling for fault-tolerant computation using maximum a posteriori (MAP) hypothesis.
Microelectronics Reliability 51(2): 485-501 (2011) |
| 2010 |
| 15 |  | Alodeep Sanyal,
Syed M. Alam,
Sandip Kundu:
BIST to Detect and Characterize Transient and Parametric Failures.
IEEE Design & Test of Computers 27(5): 50-59 (2010) |
| 14 |  | Syed M. Alam,
Robert E. Jones,
Scott Pozder,
Ritwik Chatterjee,
Shahid Rauf,
Ankur Jain:
Interstratum Connection Design Considerations for Cost-Effective 3-D System Integration.
IEEE Trans. VLSI Syst. 18(3): 450-460 (2010) |
| 13 |  | Ioannis Savidis,
Syed M. Alam,
Ankur Jain,
Scott Pozder,
Robert E. Jones,
Ritwik Chatterjee:
Electrical modeling and characterization of through-silicon vias (TSVs) for 3-D integrated circuits.
Microelectronics Journal 41(1): 9-16 (2010) |
| 2009 |
| 12 |  | Nauman H. Khan,
Syed M. Alam,
Soha Hassoun:
System-level comparison of power delivery design for 2D and 3D ICs.
3DIC 2009: 1-7 |
| 11 |  | Nauman H. Khan,
Syed M. Alam,
Soha Hassoun:
Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs.
3DIC 2009: 1-7 |
| 10 |  | Syed M. Alam,
Robert E. Jones,
Scott Pozder,
Ankur Jain:
Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology.
ISQED 2009: 569-575 |
| 9 |  | Karthikeyan Lingasubramanian,
Syed M. Alam,
Sanjukta Bhanja:
Study of Circuit-Specific Error Bounds for Fault-Tolerant Computation using Maximum a posteriori (MAP) Hypothesis
CoRR abs/0906.3282: (2009) |
| 2008 |
| 8 |  | Syed M. Alam,
Mike Ignatowski,
Yuan Xie:
Technology, CAD tools, and designs for emerging 3D integration technology.
ACM Great Lakes Symposium on VLSI 2008: 1-2 |
| 7 |  | Alodeep Sanyal,
Syed M. Alam,
Sandip Kundu:
A Built-In Self-Test Scheme for Soft Error Rate Characterization.
IOLTS 2008: 65-70 |
| 2007 |
| 6 |  | Syed M. Alam,
Robert E. Jones,
Shahid Rauf,
Ritwik Chatterjee:
Inter-Strata Connection Characteristics and Signal Transmission in Three-Dimensional (3D) Integration Technology.
ISQED 2007: 580-585 |
| 5 |  | Syed M. Alam,
Chee Lip Gan,
Carl V. Thompson,
Donald E. Troxel:
Reliability computer-aided design tool for full-chip electromigration analysis and comparison with different interconnect metallizations.
Microelectronics Journal 38(4-5): 463-473 (2007) |
| 2005 |
| 4 |  | Syed M. Alam,
Donald E. Troxel,
Carl V. Thompson:
Thermal aware cell-based full-chip electromigration reliability analysis.
ACM Great Lakes Symposium on VLSI 2005: 26-31 |
| 3 |  | Syed M. Alam,
Frank L. Wei,
Chee Lip Gan,
Carl V. Thompson,
Donald E. Troxel:
Electromigration Reliability Comparison of Cu and Al Interconnects.
ISQED 2005: 303-308 |
| 2004 |
| 2 |  | Syed M. Alam,
Chee Lip Gan,
Carl V. Thompson,
Donald E. Troxel:
Circuit Level Reliability Analysis of Cu Interconnects.
ISQED 2004: 238-243 |
| 2002 |
| 1 |  | Syed M. Alam,
Donald E. Troxel,
Carl V. Thompson:
A Comprehensive Layout Methodology and Layout-Specific Circuit Analyses for Three-Dimensional Integrated Circuits.
ISQED 2002: 246-251 |