Hussain Al-Asaad

	2010
25		Calvin Chiem, Hussain Al-Asaad: A Comparison of NMOS to PMOS Starved Buffer Implementations for the Delay Line in a PWM DC-DC Converters. CDES 2010: 10-16
24		Hussain Al-Asaad: Time-Redundant Logic-Level Protection Mechanisms from Soft Errors in Digital Systems. CDES 2010: 17-21
23		Hussain Al-Asaad: Efficient techniques for reducing error latency in on-line periodic built-in self-test. IEEE Instrum. Meas. Mag. 13(4): 28-32 (2010)
	2009
22		Hussain Al-Asaad: Detection and Isolation of Faulty Processors in Multiprocessor Systems via TMR-Based Time Redundant Task Scheduling. CDES 2009: 42-47
21		Calvin Chiem, Hussain Al-Asaad: Low Power Methodologies and Challenges for PWM DC-DC Converters. CDES 2009: 70-75
	2008
20		Jorge Campos, Hussain Al-Asaad: A Novel Mutation-Based Validation Paradigm for High-Level Hardware Descriptions. IEEE Trans. VLSI Syst. 16(11): 1499-1512 (2008)
	2007
19		Hussain Al-Asaad: Efficient Global Fault Collapsing for Combinational Library Modules. CDES 2007: 37-43
18		Ahmed Sayed, Hussain Al-Asaad: A New Statistical Approach for Glitch Estimation in Combinational Circuits. ISCAS 2007: 1641-1644
	2006
17		Ahmed Sayed, Hussain Al-Asaad: Survey and Evaluation of Low-Power Flip-Flops. CDES 2006: 77-83
16		Jorge Campos, Hussain Al-Asaad: Circuit Profiling Mechanisms for High-Level {ATPG}. MTV 2006: 9-14
	2005
15		Hussain Al-Asaad, Ganesh Valliappan, Lourdes Ramirez: A Novel Functional Testing and Verification Technique for Logic Circuits. CDES 2005: 129-135
14		Hector Arteaga, Hussain Al-Asaad: On Increasing the Observability of Modern Microprocessors. CDES 2005: 91-96
13		Hussain Al-Asaad: EGFC: An exact global fault collapsing tool for combinational circuits. Circuits, Signals, and Systems 2005: 56-61
12		Jorge Campos, Hussain Al-Asaad: Search-Space Optimizations for High-Level ATPG. MTV 2005: 84-89
	2004
11		Ahmed Sayed, Hussain Al-Asaad: Survey and Evaluation of Low-Power Full-Adder Cells. ESA/VLSI 2004: 332-338
10		Hector Arteaga, Hussain Al-Asaad: Approaches for Monitoring Vectors on Microprocessor Buses. ESA/VLSI 2004: 393-398
	2003
9		Hussain Al-Asaad, Alireza Sarvi: Fault Tolerance for Multiprocessor Systems Via Time Redundant Task Scheduling. VLSI 2003: 51-57
	2000
8		Hussain Al-Asaad, John P. Hayes: ESIM: A Multimodel Design Error and Fault Simulator for Logic Circuits. VTS 2000: 221-230
7		Hussain Al-Asaad, John P. Hayes: Logic Design Validation via Simulation and Automatic Test Pattern Generation. J. Electronic Testing 16(6): 575-589 (2000)
	1998
6		David Van Campenhout, Hussain Al-Asaad, John P. Hayes, Trevor N. Mudge, Richard B. Brown: High-level design verification of microprocessors via error modeling. ACM Trans. Design Autom. Electr. Syst. 3(4): 581-599 (1998)
5		Hussain Al-Asaad, Brian T. Murray, John P. Hayes: Online BIST for Embedded Systems. IEEE Design & Test of Computers 15(4): 17-24 (1998)
4		Hussain Al-Asaad, John P. Hayes, Brian T. Murray: Scalable Test Generators for High-Speed Datapath Circuits. J. Electronic Testing 12(1-2): 111-125 (1998)
	1995
3		Hussain Al-Asaad, John P. Hayes: Design verification via simulation and automatic test pattern generation. ICCAD 1995: 174-180
	1994
2		Hussain Al-Asaad, Mankuan Michael Vai, James Feldman: Distributed Reconfiguration of Fault Tolerant VLSI Mulipipeline Arrays with Constant Interstage Path Lengths. ICCD 1994: 75-78
	1993
1		Hussain Al-Asaad, Elias S. Manolakos: A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional Architectures. DFT 1993: 56-63

Coauthor Index

1	Hector Arteaga	[10] [14]
2	Richard B. Brown	[6]
3	David Van Campenhout	[6]
4	Jorge Campos	[12] [16] [20]
5	Calvin Chiem	[21] [25]
6	James Feldman	[2]
7	John P. Hayes	[3] [4] [5] [6] [7] [8]
8	Elias S. Manolakos	[1]
9	Trevor N. Mudge	[6]
10	Brian T. Murray	[4] [5]
11	Lourdes Ramirez	[15]
12	Alireza Sarvi	[9]
13	Ahmed Sayed	[11] [17] [18]
14	Mankuan Michael Vai	[2]
15	Ganesh Valliappan	[15]

Colors in the list of coauthors

Last update Sat May 26 04:23:17 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page