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| 2012 | ||
|---|---|---|
| 42 | Xiaoheng Chen, Shu Lin, Venkatesh Akella: Efficient Configurable Decoder Architecture for Nonbinary Quasi-Cyclic LDPC Codes. IEEE Trans. on Circuits and Systems 59-I(1): 188-197 (2012) | |
| 2011 | ||
| 41 | Christopher Nitta, Matthew K. Farrens, Venkatesh Akella: Addressing system-level trimming issues in on-chip nanophotonic networks. HPCA 2011: 122-131 | |
| 40 | Christopher Nitta, Matthew K. Farrens, Venkatesh Akella: Resilient microring resonator based photonic networks. MICRO 2011: 95-104 | |
| 39 | Christopher Nitta, Kevin Macdonald, Matthew K. Farrens, Venkatesh Akella: Inferring packet dependencies to improve trace based simulation of on-chip networks. NOCS 2011: 153-160 | |
| 38 | Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella: Memory System Optimization for FPGA-Based Implementation of Quasi-Cyclic LDPC Codes Decoders. IEEE Trans. on Circuits and Systems 58-I(1): 98-111 (2011) | |
| 37 | Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella: Hardware Implementation of a Backtracking-Based Reconfigurable Decoder for Lowering the Error Floor of Quasi-Cyclic LDPC Codes. IEEE Trans. on Circuits and Systems 58-I(12): 2931-2943 (2011) | |
| 36 | Xiaoheng Chen, Venkatesh Akella: Exploiting data-level parallelism for energy-efficient implementation of LDPC decoders and DCT on an FPGA. TRETS 4(4): 37 (2011) | |
| 2010 | ||
| 35 | Xiaohui Ye, Yawei Yin, S. J. Ben Yoo, Paul Vincent Mejia, Roberto Proietti, Venkatesh Akella: DOS: a scalable optical switch for datacenters. ANCS 2010: 24 | |
| 34 | Paul Vincent Mejia, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella: Performance Evaluation of a Multicore System with Optically Connected Memory Modules. NOCS 2010: 215-222 | |
| 33 | Eric Jung, Frank Maker III, Tang Lung Cheung, Xin Liu, Venkatesh Akella: Markov decision process (MDP) framework for software power optimization using call profiles on mobile phones. Design Autom. for Emb. Sys. 14(1): 131-159 (2010) | |
| 32 | Xiaoheng Chen, Shu Lin, Venkatesh Akella: QSN - A Simple Circular-Shift Network for Reconfigurable Quasi-Cyclic LDPC Decoders. IEEE Trans. on Circuits and Systems 57-II(10): 782-786 (2010) | |
| 2009 | ||
| 31 | Xiaoheng Chen, Jingyu Kang, Shu Lin, Venkatesh Akella: Accelerating FPGA-based emulation of quasi-cyclic LDPC codes with vector processing. DATE 2009: 1530-1535 | |
| 30 | Tang Lung Cheung, Kari Okamoto, Frank Maker III, Xin Liu, Venkatesh Akella: Markov decision process (MDP) framework for optimizing software on mobile phones. EMSOFT 2009: 11-20 | |
| 2008 | ||
| 29 | John Oliver, Rajeevan Amirtharajah, Venkatesh Akella, Frederic T. Chong: Credit-based dynamic reliability management using online wearout detection. Conf. Computing Frontiers 2008: 139-148 | |
| 28 | Amit Hadke, Tony Benavides, S. J. Ben Yoo, Rajeevan Amirtharajah, Venkatesh Akella: OCDIMM: Scaling the DRAM Memory Wall Using WDM Based Optical Interconnects. Hot Interconnects 2008: 57-63 | |
| 27 | Amit Hadke, Tony Benavides, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella: Design and evaluation of an optical CPU-DRAM interconnect. ICCD 2008: 492-497 | |
| 2007 | ||
| 26 | John Y. Oliver, Rajeevan Amirtharajah, Venkatesh Akella, Roland Geyer, Frederic T. Chong: Life Cycle Aware Computing: Reusing Silicon Technology. IEEE Computer 40(12): 56-61 (2007) | |
| 25 | John Oliver, Diana Franklin, Frederic T. Chong, Venkatesh Akella: Using Application Bisection Bandwidth to Guide Tile Size Selection for the Synchroscalar Tile-Based Architecture. T. HiPEAC 1: 259-278 (2007) | |
| 2006 | ||
| 24 | John Oliver, Ravishankar Rao, Michael Brown, Jennifer Mankin, Diana Franklin, Frederic T. Chong, Venkatesh Akella: Tile size selection for low-power tile-based architectures. Conf. Computing Frontiers 2006: 83-94 | |
| 23 | Ravishankar Rao, Justin Wenck, Diana Franklin, Rajeevan Amirtharajah, Venkatesh Akella: Segmented Bitline Cache: Exploiting Non-uniform Memory Access Patterns. HiPC 2006: 123-134 | |
| 22 | John Oliver, Ravishankar Rao, Diana Franklin, Frederic T. Chong, Venkatesh Akella: Synchroscalar: Evaluation of an embedded, multi-core architecture for media applications. J. Embedded Computing 2(2): 157-166 (2006) | |
| 2005 | ||
| 21 | Venkatesh Akella, Mihaela van der Schaar, Wen-Fu Kao: Proactive Energy Optimization Algorithms for Wavelet-Based Video Codecs on Power-Aware Processors. ICME 2005: 566-569 | |
| 2004 | ||
| 20 | Mihaela van der Schaar, Deepak S. Turaga, Venkatesh Akella: Rate-distortion-complexity adaptive video compression and streaming. ICIP 2004: 2051-2054 | |
| 19 | John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong: Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor. ISCA 2004: 150-161 | |
| 18 | John Oliver, Venkatesh Akella, Frederic T. Chong: Efficient orchestration of sub-word parallelism in media processors. SPAA 2004: 225-234 | |
| 2003 | ||
| 17 | John Oliver, Venkatesh Akella: Improving DSP Performance with a Small Amount of Field Programmable Logic. FPL 2003: 520-532 | |
| 16 | John Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. Chong: Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture. PACS 2003: 73-85 | |
| 15 | S. J. Ben Yoo, Fei Xue, Y. Bansal, J. Taylor, Zhong Pan, Jing Cao, Minyong Jeon, T. Nady, G. Goncher, K. Boyer, Kari Okamoto, S. Kamei, Venkatesh Akella: High-performance optical-label switching packet routers and smart edge routers for the next-generation Internet. IEEE Journal on Selected Areas in Communications 21(7): 1041-1051 (2003) | |
| 2001 | ||
| 14 | Tony Werner, Venkatesh Akella: An Asynchronous Superscalar Architecture for Exploiting Instruction-Level Parallelism. ASYNC 2001: 140-151 | |
| 1999 | ||
| 13 | Nithya Raghavan, Venkatesh Akella, Smita Bakshi: Automatic Insertion of Gated Clocks at Register Transfer Level. VLSI Design 1999: 48-54 | |
| 1998 | ||
| 12 | Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo: Asynchronous Comparison-Based Decoders for Delay-Insensitive Codes. IEEE Trans. Computers 47(7): 802-811 (1998) | |
| 11 | Dave Johnson, Venkatesh Akella, Bret Stott: Micropipelined asynchronous discrete cosine transform (DCT/IDCT) processor. IEEE Trans. VLSI Syst. 6(4): 731-740 (1998) | |
| 1997 | ||
| 10 | Tony Werner, Venkatesh Akella: Asynchronous Processor Survey. IEEE Computer 30(11): 67-76 (1997) | |
| 1996 | ||
| 9 | Venkatesh Akella, Nitin H. Vaidya, G. Robert Redinbo: Limitations of VLSI Implementation of Delay-Insensitive Codes. FTCS 1996: 208-217 | |
| 1995 | ||
| 8 | Bret Stott, Dave Johnson, Venkatesh Akella: Asynchronous 2-D discrete cosine transform core processor. ICCD 1995: 380-385 | |
| 1994 | ||
| 7 | Prabhakar Kudva, Ganesh Gopalakrishnan, Erik Brunvand, Venkatesh Akella: Performance Analysis and Optimization of Asynchronous Circuits. ICCD 1994: 221-224 | |
| 6 | Venkatesh Akella, Ganesh Gopalakrishnan: Specification and Validation of Control-Intensive IC's in hopCP. IEEE Trans. Software Eng. 20(6): 405-423 (1994) | |
| 5 | Venkatesh Akella, Ganesh Gopalakrishnan: CFSIM: A Concurrent Compiled Code Functional Simulator for hopCP. Int. Journal in Computer Simulation 4(4): 0- (1994) | |
| 4 | Ganesh Gopalakrishnan, Venkatesh Akella: High-level optimizations in compiling process descriptions to asynchronous circuits. VLSI Signal Processing 7(1-2): 33-45 (1994) | |
| 1993 | ||
| 3 | Ganesh Gopalakrishnan, Venkatesh Akella: A transformational approach to asynchronous high-level synthesis. VLSI 1993: 201-210 | |
| 1992 | ||
| 2 | Venkatesh Akella, Ganesh Gopalakrishnan: SHILPA: a high-level synthesis system for self-timed circuits. ICCAD 1992: 587-591 | |
| 1989 | ||
| 1 | Ganesh Gopalakrishnan, Narayana Mani, Venkatesh Akella: Parallel Composition of Lockstep Synchronous Processes for Hardware Validation: Divide-and-Conquer Composition. Automatic Verification Methods for Finite State Systems 1989: 374-382 | |
Colors in the list of coauthors
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