Yasutoshi Aibara

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2012

2 Sebastian Hoyos, Cheongyuen W. Tsang, Johan Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic: A 15 MHz to 600 MHz, 20 mW, 0.38 mm² Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS. IEEE Trans. VLSI Syst. 20(3): 564-568 (2012)

2006

1 Yasutoshi Aibara, Eiki Imaizumi, Hiroaki Takagishi, Tatsuji Matsuura: A Novel False Lock Detection Technique for a Wide Frequency Range Delay-Locked Loop. IEICE Transactions 89-A(2): 385-390 (2006)

	2012
2		Sebastian Hoyos, Cheongyuen W. Tsang, Johan Vanderhaegen, Yun Chiu, Yasutoshi Aibara, Haideh Khorramabadi, Borivoje Nikolic: A 15 MHz to 600 MHz, 20 mW, 0.38 mm² Split-Control, Fast Coarse Locking Digital DLL in 0.13 µ m CMOS. IEEE Trans. VLSI Syst. 20(3): 564-568 (2012)
	2006
1		Yasutoshi Aibara, Eiki Imaizumi, Hiroaki Takagishi, Tatsuji Matsuura: A Novel False Lock Detection Technique for a Wide Frequency Range Delay-Locked Loop. IEICE Transactions 89-A(2): 385-390 (2006)

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