 | 2010 |
|---|
| 5 |       | Mahmoud Reza Ahmadi,
Amir Amirkhany,
Ramesh Harjani:
A 5 Gbps 0.13 μ m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links.
J. Solid-State Circuits 45(8): 1533-1541 (2010) |
| 2009 |
|---|
| 4 | | Mahmoud Reza Ahmadi,
Amir Amirkhany,
Ramesh Harjani:
A 5Gbps 0.13μm CMOS pilot-based clock and data recovery scheme for high-speed links.
CICC 2009: 125-128 |
| 2008 |
|---|
| 3 | | Mahmoud Reza Ahmadi,
Jaekyun Moon,
Ramesh Harjani:
Constrained Partial Response Receivers for High-Speed Links.
IEEE Trans. on Circuits and Systems 55-II(10): 1006-1010 (2008) |
| 2 | | Kin-Joe Sham,
Shubha Bommalingaiahnapallya,
Mahmoud Reza Ahmadi,
Ramesh Harjani:
A 3, times, 5-Gb/s Multilane Low-Power 0.18-muhbox m CMOS Pseudorandom Bit Sequence Generator.
IEEE Trans. on Circuits and Systems 55-II(5): 432-436 (2008) |
| 2007 |
|---|
| 1 | | Shubha Bommalingaiahnapallya,
Kin-Joe Sham,
Mahmoud Reza Ahmadi,
Ramesh Harjani:
High-Speed Circuits for a Multi-Lane 12 Gbps CMOS PRBS Generator.
ISCAS 2007: 3896-3899 |
Data released under the ODC-BY 1.0 license — See also our legal information page