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Vishwani D. Agrawal Coauthor index pubzone.org

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DBLP keys2012
313Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Srimat T. Chakradhar: 25th International Conference on VLSI Design, VLSID 2012, Hyderabad, India, January 7-11, 2012 IEEE 2012
312Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Keynote Talk: A History of the VLSI Design Conference. VLSI Design 2012: 1-2
311Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPriyadharshini Shanmugasundaram, Vishwani D. Agrawal: Externally Tested Scan Circuit with Built-In Activity Monitor and Adaptive Test Clock. VLSI Design 2012: 448-453
310Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 28(1): 1 (2012)
309Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 28(2): 151-152 (2012)
308Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMohammed Ashfaq Shukoor, Vishwani D. Agrawal: Diagnostic Test Set Minimization and Full-Response Fault Dictionary. J. Electronic Testing 28(2): 177-187 (2012)
2011
307Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuraj Sindia, Vishwani D. Agrawal, Virendra Singh: Test and Diagnosis of Analog Circuits Using Moment Generating Functions. Asian Test Symposium 2011: 371-376
306Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYu Zhang, Vishwani D. Agrawal: Reduced complexity test generation algorithms for transition fault diagnosis. ICCD 2011: 96-101
305Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKyungseok Kim, Vishwani D. Agrawal: Minimum energy CMOS design with dual subthreshold supply and multiple logic-level gates. ISQED 2011: 689-694
304Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKyungseok Kim, Vishwani D. Agrawal: True Minimum Energy Design Using Dual Below-Threshold Supply Voltages. VLSI Design 2011: 292-297
303Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPriyadharshini Shanmugasundaram, Vishwani D. Agrawal: Dynamic scan clock control for test time reduction maintaining peak power limit. VTS 2011: 248-253
302Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuraj Sindia, Vishwani D. Agrawal, Virendra Singh: Non-linear analog circuit test and diagnosis under process variation using V-Transform coefficients. VTS 2011: 64-69
301Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 27(1): 1-2 (2011)
300Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 27(2): 95 (2011)
299Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 27(3): 219 (2011)
298Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 27(4): 425-426 (2011)
297Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 27(5): 579 (2011)
296Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 27(6): 681-682 (2011)
295Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKyungseok Kim, Vishwani D. Agrawal: Ultra Low Energy CMOS Logic Using Below-Threshold Dual-Voltage Supply. J. Low Power Electronics 7(4): 460-470 (2011)
2010
294Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYu Zhang, Vishwani D. Agrawal: A diagnostic test generation system and a coverage metric. European Test Symposium 2010: 254
293Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLFan Wang, Vishwani D. Agrawal: Soft error rate determination for nanoscale sequential logic. ISQED 2010: 225-230
292Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYu Zhang, Vishwani D. Agrawal: A diagnostic test generation system. ITC 2010: 360-368
291Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuraj Sindia, Virendra Singh, Vishwani D. Agrawal: Parametric Fault Diagnosis of Nonlinear Analog Circuits Using Polynomial Coefficients. VLSI Design 2010: 288-293
290Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNitin Yogi, Vishwani D. Agrawal: Application of signal and noise theory to digital VLSI testing. VTS 2010: 215-220
289Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 26(1): 1-2 (2010)
288Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 26(3): 293 (2010)
287Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 26(4): 401 (2010)
286Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 26(5): 495 (2010)
285Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 26(6): 595-596 (2010)
2009
284Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuraj Sindia, Virendra Singh, Vishwani D. Agrawal: Polynomial coefficient based DC testing of non-linear analog circuits. ACM Great Lakes Symposium on VLSI 2009: 69-74
283Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuraj Sindia, Virendra Singh, Vishwani D. Agrawal: Multi-tone Testing of Linear and Nonlinear Analog Circuits Using Polynomial Coefficients. Asian Test Symposium 2009: 63-68
282Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMohammed Ashfaq Shukoor, Vishwani D. Agrawal: A Two Phase Approach for Minimal Diagnostic Test Set Generation. European Test Symposium 2009: 115-120
281Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJaynarayan T. Tudu, Erik Larsson, Virendra Singh, Vishwani D. Agrawal: On Minimization of Peak Power for Scan Circuit during Test. European Test Symposium 2009: 25-30
280Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWei Jiang, Vishwani D. Agrawal: Designing Variation-tolerance in Mixed-signal Components of a System-on-chip. ISCAS 2009: 2313-2316
279Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJins D. Alexander, Vishwani D. Agrawal: Algorithms for Estimating Number of Glitches and Dynamic Power in CMOS Circuits with Delay Variations. ISVLSI 2009: 127-132
278Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLFan Wang, Vishwani D. Agrawal: Soft Error Rates with Inertial and Logical Masking. VLSI Design 2009: 459-464
277Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSreekumar Menon, Adit D. Singh, Vishwani D. Agrawal: Output Hazard-Free Transition Delay Fault Test Generation. VTS 2009: 97-102
276Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Variable Input Delay CMOS Logic for Low Power Design. IEEE Trans. VLSI Syst. 17(10): 1534-1545 (2009)
275Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 25(1): 1 (2009)
274Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 25(4-5): 209 (2009)
273Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 25(6): 285 (2009)
2008
272Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: A tutorial on test power. ISLPED 2008: 237-238
271Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLWei Jiang, Vishwani D. Agrawal: Built-in Self-Calibration of On-chip DAC and ADC. ITC 2008: 1-10
270Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLFan Wang, Vishwani D. Agrawal: Single Event Upset: An Embedded Tutorial. VLSI Design 2008: 429-434
269Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYuanlin Lu, Vishwani D. Agrawal: Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation. VLSI Design 2008: 527-532
268Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRajamani Sethuram, Michael L. Bushnell, Vishwani D. Agrawal: Fault Nodes in Implication Graph for Equivalence/Dominance Collapsing, and Identifying Untestable and Independent Faults. VTS 2008: 329-335
267Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 24(1-3): 1 (2008)
266Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 24(4): 321 (2008)
265Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 24(5): 421 (2008)
264Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 24(6): 505-506 (2008)
2007
263Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoumitra Bose, Hillary Grimes, Vishwani D. Agrawal: Delay fault simulation with bounded gate delay mode. ITC 2007: 1-10
262Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoumitra Bose, Vishwani D. Agrawal: Estimating stuck fault coverage in sequential logic using state traversal and entropy analysis. ITC 2007: 1-10
261Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLOmar I. Khan, Michael L. Bushnell, Suresh Kumar Devanathan, Vishwani D. Agrawal: SPARTAN: a spectral and information theoretic approach to partial-scan. ITC 2007: 1-10
260Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYuanlin Lu, Vishwani D. Agrawal: Statistical Leakage and Timing Optimization for Submicron Process Variation. VLSI Design 2007: 439-444
259Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLNitin Yogi, Vishwani D. Agrawal: Spectral RTL Test Generation for Microprocessors. VLSI Design 2007: 473-478
258Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKalyana R. Kantipudi, Vishwani D. Agrawal: A Reduced Complexity Algorithm for Minimizing N-Detect Tests. VLSI Design 2007: 492-497
257Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoumitra Bose, Vishwani D. Agrawal: Delay Test Quality Evaluation Using Bounded Gate Delays. VTS 2007: 23-28
256Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLan Rao, Michael L. Bushnell, Vishwani D. Agrawal: Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. IEEE Trans. VLSI Syst. 15(11): 1245-1255 (2007)
255Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 23(1): 5 (2007)
254Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 23(2-3): 111 (2007)
253Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 23(5): 369 (2007)
252Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 23(6): 465 (2007)
2006
251Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLFei Hu, Vishwani D. Agrawal: Input-specific dynamic power optimization for VLSI circuits. ISLPED 2006: 232-237
250Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoumitra Bose, Vishwani D. Agrawal: Fault Coverage Estimation for Non-Random Functional Input Sequences. ITC 2006: 1-10
249Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Soumitra Bose, Vijay Gangaram: Upper Bounding Fault Coverage by Structural Analysis and Signal Monitoring. VTS 2006: 88-93
248Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 22(1): 5 (2006)
247Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 22(2): 111 (2006)
246Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 22(4-6): 307 (2006)
245Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Transistor Sizing of Logic Gates to Maximize Input Delay Variability. J. Low Power Electronics 2(1): 121-128 (2006)
244Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYuanlin Lu, Vishwani D. Agrawal: CMOS Leakage and Glitch Minimization for Power-Performance Tradeoff. J. Low Power Electronics 2(3): 378-387 (2006)
2005
243Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLFei Hu, Vishwani D. Agrawal: Dual-transition glitch filtering in probabilistic waveform power estimation. ACM Great Lakes Symposium on VLSI 2005: 357-360
242Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Alok S. Doshi: Concurrent Test Generation. Asian Test Symposium 2005: 294-299
241Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRaja K. K. R. Sandireddy, Vishwani D. Agrawal: Diagnostic and Detection Fault Collapsing for Multiple Output Circuits. DATE 2005: 1014-1019
240Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLFei Hu, Vishwani D. Agrawal: Enhanced Dual-Transition Probabilistic Power Estimation with Selective Supergate Analysis. ICCD 2005: 366-372
239Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnand S. Mudlapur, Vishwani D. Agrawal, Adit D. Singh: A random access scans architecture to reduce hardware overhead. ITC 2005: 9
238Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYuanlin Lu, Vishwani D. Agrawal: Leakage and Dynamic Glitch Power Minimization Using Integer Linear Programming for Vth Assignment and Path Balancing. PATMOS 2005: 217-226
237Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Design of Variable Input Delay Gates for Low Dynamic Power Circuits. PATMOS 2005: 436-445
236Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Variable Input Delay CMOS Logic for Low Power Design. VLSI Design 2005: 598-605
235Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell: Using Contrapositive Law in an Implication Graph to Identify Logic Redundancies. VLSI Design 2005: 723-729
234Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja: Combinational automatic test pattern generation for acyclic sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 24(6): 948-956 (2005)
233Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 21(1): 5 (2005)
232Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 21(2): 111 (2005)
231Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 21(3): 199 (2005)
230Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 21(5): 459 (2005)
229Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 21(6): 567 (2005)
2004
228Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJunwu Zhang, Michael L. Bushnell, Vishwani D. Agrawal: On Random Pattern Generation with the Selfish Gene Algorithm for Testing Digital Sequential Circuits. ITC 2004: 617-626
227Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. VLSI Design 2004: 1035-1040
226Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: A Tuturial on the Emerging Nanotechnology Devices. VLSI Design 2004: 343-360
225Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: 1985 to 1987: My years with D&T. IEEE Design & Test of Computers 21(3): 173-174 (2004)
224Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell: A New Classification of Path-Delay Fault Testability in Terms of Stuck-at Faults. J. Comput. Sci. Technol. 19(6): 955-964 (2004)
223Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 20(1): 5-6 (2004)
222Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 20(2): 127 (2004)
221Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 20(3): 219 (2004)
220Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 20(4): 327 (2004)
219Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 20(5): 459 (2004)
218Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 20(6): 571 (2004)
2003
217Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, A. V. S. S. Prasad, Madhusudan V. Atre: Fault Collapsing via Functional Dominance. ITC 2003: 274-280
216Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Dong Hyun Baik, Yong Chang Kim, Kewal K. Saluja: Exclusive Test and its Applications to Fault Diagnosis. VLSI Design 2003: 143-148
215Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishal J. Mehta, Kunal K. Dave, Vishwani D. Agrawal, Michael L. Bushnell: A Fault-Independent Transitive Closure Algorithm for Redundancy Identification. VLSI Design 2003: 149-154
214Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLan Rao, Michael L. Bushnell, Vishwani D. Agrawal: New Graphical IDDQ Signatures Reduce Defect Level and Yield Loss. VLSI Design 2003: 353-360
213Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTezaswi Raja, Vishwani D. Agrawal, Michael L. Bushnell: Minimum Dynamic Power CMOS Circuit Design by a Reduced Constraint Set Linear Program. VLSI Design 2003: 527-532
212Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul: A test evaluation technique for VLSI circuits using register-transfer level fault modeling. IEEE Trans. on CAD of Integrated Circuits and Systems 22(8): 1104-1113 (2003)
211Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 19(1): 5 (2003)
210Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 19(2): 95 (2003)
209Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 19(3): 219 (2003)
208Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 19(4): 363 (2003)
207Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 19(6): 607 (2003)
2002
206Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVivek Gaur, Vishwani D. Agrawal, Michael L. Bushnell: A New Transitive Closure Algorithm with Application to Redundancy Identification. DELTA 2002: 496-500
205Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAditya D. Sathe, Michael L. Bushnell, Vishwani D. Agrawal: Analog Macromodeling of Capacitive Coupling Faults in Digital Circuit Interconnects. ITC 2002: 375-383
204Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLA. V. S. S. Prasad, Vishwani D. Agrawal, Madhusudan V. Atre: A New Algorithm for Global Fault Collapsing into Equivalence and Dominance Sets. ITC 2002: 391-397
203Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Michael L. Bushnell: Electronic Testing for SOC Designers (Tutorial Abstract). VLSI Design 2002: 20
202Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja: Multiple Faults: Modeling, Simulation and Test. VLSI Design 2002: 592-597
201Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 18(1): 5 (2002)
200Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAshish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal: State and Fault Information for Compaction-Based Test Generation. J. Electronic Testing 18(1): 63-72 (2002)
199Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 18(2): 103-104 (2002)
198Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 18(3): 255 (2002)
197Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 18(4-5): 359 (2002)
196Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 18(6): 567-568 (2002)
2001
195Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAshish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal: Efficient spectral techniques for sequential ATPG. DATE 2001: 204-208
194Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYong Chang Kim, Vishwani D. Agrawal, Kewal K. Saluja: Combinational test generation for various classes of acyclic sequential circuits. ITC 2001: 1078-1087
193Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal: Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. VLSI Design 2001: 143-148
192Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAshish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal: Novel Spectral Methods for Built-In Self-Test in a System-on-a-Chip Environment. VTS 2001: 163-168
191Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 17(2): 79 (2001)
190Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 17(3-4): 203 (2001)
189Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 17(5): 367 (2001)
188Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 17(6): 455 (2001)
2000
187Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHuan-Chih Tsai, Kwang-Ting Cheng, Vishwani D. Agrawal: A testability metric for path delay faults and its application. ASP-DAC 2000: 593-598
186Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAshish Giani, Shuo Sheng, Michael S. Hsiao, Vishwani D. Agrawal: Compaction-based test generation using state and fault information. Asian Test Symposium 2000: 159-164
185Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKwang-Ting Cheng, Vishwani D. Agrawal, Jing-Yang Jou, Li-C. Wang, Chi-Feng Wu, Shianling Wu: Collaboration between Industry and Academia in Test Research. Asian Test Symposium 2000: 17-
184Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Kwang-Ting Cheng: Testing in the Fourth Dimension. Asian Test Symposium 2000: 2-
183Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJosé T. de Sousa, Vishwani D. Agrawal: Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. DATE 2000: 640-644
182Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul: Register-transfer level fault modeling and test evaluation techniques for VLSI circuits. ITC 2000: 940-949
181Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Choice of Tests for Logic Verification and Equivalence Checking. VLSI Design 2000: 306-311
180Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Path delay fault simulation of sequential circuits. IEEE Trans. VLSI Syst. 8(2): 223-228 (2000)
179Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Improving path delay testability of sequential circuits. IEEE Trans. VLSI Syst. 8(6): 736-741 (2000)
178Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 16(1-2): 5 (2000)
177Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 16(3): 163 (2000)
176Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 16(4): 315 (2000)
175Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 16(5): 403-404 (2000)
174Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMarwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell, Carlos G. Parodi: False-Path Removal Using Delay Fault Simulation. J. Electronic Testing 16(5): 463-476 (2000)
173Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 16(6): 571 (2000)
1999
172Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLYong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal: A Correlation Matrix Method of Clock Partitioning for Sequential Circuit Testability. Great Lakes Symposium on VLSI 1999: 300-
171no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Panel: Increasing test coverage in a VLSI desgin course. ITC 1999: 1131
170Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Michael L. Bushnell, Ganapathy Parthasarathy, Rajesh Ramadoss: Digital Circuit Design for Minimum Transient Energy and a Linear Programming Method. VLSI Design 1999: 434-439
169Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: A Test Generator for Segment Delay Faults. VLSI Design 1999: 484-491
168Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhashis Majumder, Bhargab B. Bhattacharya, Vishwani D. Agrawal, Michael L. Bushnell: A Complete Characterization of Path Delay Faults through Stuck-at Faults. VLSI Design 1999: 492-497
167Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPradip A. Thaker, Vishwani D. Agrawal, Mona E. Zaghloul: Validation Vector Grade (VVG): A New Coverage Metric for Validation and Test. VTS 1999: 182-188
166Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 14(1-2): 7 (1999)
165Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 14(3): 187-188 (1999)
164Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 15(1-2): 5 (1999)
163Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 15(3): 215 (1999)
1998
162Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMarwan A. Gharaybeh, Vishwani D. Agrawal, Michael L. Bushnell: False-Path Removal Using Delay Fault Simulation. Asian Test Symposium 1998: 82-87
161Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Sharad C. Seth: Mutually Disjoint Signals and Probability Calculation in Digital Circuits. Great Lakes Symposium on VLSI 1998: 307-312
160Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCarlos G. Parodi, Vishwani D. Agrawal, Michael L. Bushnell, Shianling Wu: A non-enumerative path delay fault simulator for sequential circuits. ITC 1998: 934-943
159Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPramit Chavda, James Jacob, Vishwani D. Agrawal: Optimizing Logic Design Using Boolean Transforms. VLSI Design 1998: 218-221
158Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnanta K. Majhi, Vishwani D. Agrawal: Mixed-Signal Test. VLSI Design 1998: 285-288
157Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnanta K. Majhi, Vishwani D. Agrawal: Tutorial: Delay Fault Models and Coverage. VLSI Design 1998: 364-369
156Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhashis Majumder, Michael L. Bushnell, Vishwani D. Agrawal: Path Delay Testing: Variable-Clock Versus Rated-Clock. VLSI Design 1998: 470-475
155Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSubhashis Majumder, Vishwani D. Agrawal, Michael L. Bushnell: On Delay-Untestable Paths and Stuck-Fault Redundancy. VTS 1998: 194-199
154Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. Design Autom. for Emb. Sys. 3(2-3): 115-116 (1998)
153Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: Deriving Logic Systems for Path Delay Test Generation. IEEE Trans. Computers 47(8): 829-846 (1998)
152Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMarwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: The path-status graph with application to delay fault simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 17(4): 324-332 (1998)
151Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMarwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: A parallel-vector concurrent-fault simulator and generation of single-input-change tests for path-delay faults. IEEE Trans. on CAD of Integrated Circuits and Systems 17(9): 873-876 (1998)
150Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Design of mixed-signal systems for testability. Integration 26(1-2): 141-150 (1998)
149Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 12(1-2): 5 (1998)
148Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 12(3): 167 (1998)
147Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas: Statistical Delay Fault Coverage Estimation for Synchronous Sequential Circuits. J. Electronic Testing 12(3): 239-254 (1998)
146Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 13(1): 5 (1998)
145Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 13(2): 75 (1998)
144Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 13(3): 219 (1998)
1997
143Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: Fast identification of untestable delay faults using implications. ICCAD 1997: 642-647
142Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoumitra Bose, Vishwani D. Agrawal, Thomas G. Szymanski: Algorithms for Switch Level Delay Fault Simulation. ITC 1997: 982-991
141Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTapan J. Chakraborty, Vishwani D. Agrawal: Effective Path Selection for Delay Fault Testing of Sequential Circuits. ITC 1997: 998-1003
140Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Low-Power Design by Hazard Filtering. VLSI Design 1997: 193-197
139Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJames Jacob, P. Srinivas Sivakumar, Vishwani D. Agrawal: Adder and Comparator Synthesis with Exclusive-OR Transform of Inputs. VLSI Design 1997: 514-515
138Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMandyam-Komar Srinivas, Michael L. Bushnell, Vishwani D. Agrawal: Flags and Algebra for Sequential Circuit VNR Path Delay Fault Test Generation. VLSI Design 1997: 88-94
137Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian: Power Dissipation During Testing: Should We Worry About it? VTS 1997: 456-457
136Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRichard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal: Scheduling tests for VLSI systems under power constraints. IEEE Trans. VLSI Syst. 5(2): 175-185 (1997)
135Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: On variable clock methods for path delay testing of sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1237-1249 (1997)
134Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal: Redundancy removal and test generation for circuits with non-Boolean primitives. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1370-1377 (1997)
133Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKeerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell, Janak H. Patel: Improving a nonenumerative method to estimate path delay fault coverage. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 759-762 (1997)
132Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 10(1-2): 5 (1997)
131Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 10(3): 171 (1997)
130Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 11(1): 5 (1997)
129Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMarwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. J. Electronic Testing 11(1): 55-67 (1997)
128Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 11(2): 107 (1997)
127Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 11(3): 195 (1997)
1996
126Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Michael L. Bushnell, Qing Lin: Redundancy Identification Using Transitive Closure. Asian Test Symposium 1996: 4-9
125Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal: Improving Circuit Testability by Clock Control. Great Lakes Symposium on VLSI 1996: 288-293
124Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: SIGMA: a simulator for segment delay faults. ICCAD 1996: 502-508
123Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMarwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: An Exact Non-Enumerative Fault Simulator for Path-Delay Faults. ITC 1996: 276-285
122Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Ronald D. Blanton, Maurizio Damiani: Synthesis of Self-Testing Finite State Machines from High-Level Specifications. ITC 1996: 757-766
121Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLLakshminarayana Pappu, Michael L. Bushnell, Vishwani D. Agrawal, Mandyam-Komar Srinivas: Statistical path delay fault coverage estimation for synchronous sequential circuits. VLSI Design 1996: 290-295
120Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, David Lee: Characteristic polynomial method for verification and test of combinational circuits. VLSI Design 1996: 341-342
119Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnanta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal: On test coverage of path delay faults. VLSI Design 1996: 418-421
118Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: Improving accuracy in path delay fault coverage estimation. VLSI Design 1996: 422-425
117Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMarwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: Parallel concurrent path-delay fault simulation using single-input change patterns. VLSI Design 1996: 426-431
116Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTapan J. Chakraborty, Vishwani D. Agrawal: Design for high-speed testability of stuck-at faults. VLSI Design 1996: 53-56
115Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Science, Technology, and the Indian Society. VLSI Design 1996: 6-9
114Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKeerthi Heragu, Janak H. Patel, Vishwani D. Agrawal: Segment delay faults: a new fault model. VTS 1996: 32-41
113no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: 1995 Asian Test Symposium carves a niche. IEEE Design & Test of Computers 13(2): 3- (1996)
112Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal: Functional test generation for synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 15(7): 831-843 (1996)
111Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 8(2): 111 (1996)
110Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 9(1-2): 5 (1996)
1995
109Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Bernard Courtois, Fumiyasu Hirose, Sandip Kundu, Chung-Len Lee, Yinghua Min, P. Pal Chaudhuri: Panel: New Research Problems in the Emerging Test Technology. Asian Test Symposium 1995: 189-
108Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell: Functional test generation for path delay faults. Asian Test Symposium 1995: 339-345
107Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoumitra Bose, Vishwani D. Agrawal: Sequential logic path delay test generation by symbolic analysis. Asian Test Symposium 1995: 353-
106Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJames Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal: An adaptive distributed algorithm for sequential circuit test generation. EURO-DAC 1995: 236-241
105Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMarwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal: Classification and Test Generation for Path-Delay Faults Using Single Stuck-Fault Tests. ITC 1995: 139-148
104Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Tapan J. Chakraborty: High-Performance Circuit Testing with Slow-Speed Testers. ITC 1995: 302-310
103Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAnanta K. Majhi, James Jacob, Lalit M. Patnaik, Vishwani D. Agrawal: An efficient automatic test generation system for path delay faults in combinational circuits. VLSI Design 1995: 161-165
102Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKeerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell: Statistical methods for delay fault coverage analysis. VLSI Design 1995: 166-170
101Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJames Sienicki, Michael L. Bushnell, Prathima Agrawal, Vishwani D. Agrawal: An asynchronous algorithm for sequential circuit test generation on a network of workstations. VLSI Design 1995: 36-41
100Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTapan J. Chakraborty, Vishwani D. Agrawal: Robust testing for stuck-at faults. VLSI Design 1995: 42-46
99Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal: Functional test generation for non-scan sequential circuits. VLSI Design 1995: 47-52
98Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTapan J. Chakraborty, Vishwani D. Agrawal: Simulation of at-speed tests for stuck-at faults. VTS 1995: 216-220
97Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDebashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal: Test Generation for Path Delay Faults Using Binary Decision Diagrams. IEEE Trans. Computers 44(3): 434-447 (1995)
96Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: A partition and resynthesis approach to testable design of large circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(10): 1268-1276 (1995)
95Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKeerthi Heragu, Vishwani D. Agrawal, Michael L. Bushnell: Fault coverage estimation by test vector sampling. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 590-596 (1995)
94Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Mahesh A. Iyer, Vishwani D. Agrawal: Energy models for delay testing. IEEE Trans. on CAD of Integrated Circuits and Systems 14(6): 728-739 (1995)
93Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: Test function embedding algorithms with application to interconnected finite state machines. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1115-1127 (1995)
92Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Srimat T. Chakradhar: Combinational ATPG theorems for identifying untestable faults in sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(9): 1155-1160 (1995)
91Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 6(1): 5-6 (1995)
90Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 6(2): 147 (1995)
89Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 6(3): 263 (1995)
88Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial - Special issue on partial scan design. J. Electronic Testing 7(1-2): 5-6 (1995)
87Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal: An exact algorithm for selecting partial scan flip-flops. J. Electronic Testing 7(1-2): 83-93 (1995)
86Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 7(3): 143 (1995)
1994
85no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLErnst G. Ulrich, Vishwani D. Agrawal, Jack H. Arabian: Concurrent and comparative discrete event simulation. Kluwer 1994: I-XIII, 1-186
84Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKeerthi Heragu, Michael L. Bushnell, Vishwani D. Agrawal: An Efficient Path Delay Fault Coverage Estimator. DAC 1994: 516-521
83Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Arun Balakrishnan, Vishwani D. Agrawal: An Exact Algorithm for Selecting Partial Scan Flip-Flops. DAC 1994: 81-86
82no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: A Test Function Architecture for Interconnected Finite State Machines. VLSI Design 1994: 113-116
81no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRichard M. Chou, Kewal K. Saluja, Vishwani D. Agrawal: Power Constraint Scheduling of Tests. VLSI Design 1994: 271-274
80no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLP. R. Suresh Kumar, James Jacob, Mandyam-Komar Srinivas, Vishwani D. Agrawal: An Improved Deductive Fault Simulator. VLSI Design 1994: 307-310
79Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 5(1): 5 (1994)
78Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Energy minimization and design for testability. J. Electronic Testing 5(1): 57-66 (1994)
77Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 5(2-3): 127 (1994)
76Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: A tale of two designs: the cheapest and the most economic. J. Electronic Testing 5(2-3): 131-135 (1994)
75Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 5(4): 317 (1994)
1993
74Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPrathima Agrawal, Vishwani D. Agrawal, Joan Villoldo: Sequential Circuit Test Generation on a Distributed System. DAC 1993: 107-111
73Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Design for Testability for Path Delay faults in Sequential Circuits. DAC 1993: 453-457
72no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPrathima Agrawal, Vishwani D. Agrawal, Joan Villoldo: Test Pattern Generation for Sequential Circuits on a Network of Workstations. HPDC 1993: 114-120
71Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: Generation of Compact Delay Tests by Multiple-Path Activation. ITC 1993: 714-723
70Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSuman Kanjilal, Srimat T. Chakradhar, Vishwani D. Agrawal: A Synthesis Approach to Design for Testability. ITC 1993: 754-763
69no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: A Path Delay Fault Simulator for Sequential Circuits. VLSI Design 1993: 269-274
68Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPrathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth: Generating Tests for Delay Faults in Nonscan Circuits. IEEE Design & Test of Computers 10(1): 20-28 (1993)
67Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja: A Tutorial on Built-in Self-Test. I. Principles. IEEE Design & Test of Computers 10(1): 73-82 (1993)
66Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja: A Tutorial on Built-In Self-Test, Part 2: Applications. IEEE Design & Test of Computers 10(2): 69-77 (1993)
65Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: Path delay fault simulation of sequential circuits. IEEE Trans. VLSI Syst. 1(4): 453-461 (1993)
64Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLD. Das, Sharad C. Seth, Vishwani D. Agrawal: Accurate computation of field reject ratio based on fault latency. IEEE Trans. VLSI Syst. 1(4): 537-545 (1993)
63Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler: A transitive closure algorithm for test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1015-1028 (1993)
62Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 4(1): 5 (1993)
61Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal: Finite state machine synthesis with fault tolerant test function. J. Electronic Testing 4(1): 57-69 (1993)
60Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 4(2): 123 (1993)
59Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 4(3): 199 (1993)
58Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSoumitra Bose, Prathima Agrawal, Vishwani D. Agrawal: The optimistic update theorem for path delay testing in sequential circuits. J. Electronic Testing 4(3): 285-290 (1993)
57Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 4(4): 295 (1993)
1992
56Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDebashis Bhattacharya, Prathima Agrawal, Vishwani D. Agrawal: Delay Fault Test Generation for Scan/Hold Circuits Using Boolean Expressions. DAC 1992: 159-164
55Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLTapan J. Chakraborty, Vishwani D. Agrawal, Michael L. Bushnell: Delay Fault Models and Test Generation for Random Logic Sequential Circuits. DAC 1992: 165-172
54Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Suman Kanjilal, Vishwani D. Agrawal: Finite State Machine Synthesis with Fault Tolerant Test Function. DAC 1992: 562-567
53Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLMandyam-Komar Srinivas, James Jacob, Vishwani D. Agrawal: Finite State Machine Testing Based on Growth and Dissappearance Faults. FTCS 1992: 238-245
52Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKwang-Ting Cheng, Vishwani D. Agrawal: Initializability Consideration in Sequential Machine Synthesis. IEEE Trans. Computers 41(3): 374-379 (1992)
51Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Srimat T. Chakradhar: Performance Analysis of Synchronized Iterative Algorithms on Multiprocessor Systems. IEEE Trans. Parallel Distrib. Syst. 3(6): 739-746 (1992)
50Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 3(2): 105 (1992)
49Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLErnst G. Ulrich, Karen Lentz, Jack H. Arabian, Michael Gustin, Vishwani D. Agrawal, Pier Luca Montessoro: The Comparative and Concurrent Simulation of discrete-event experiments. J. Electronic Testing 3(2): 107-118 (1992)
48Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJames Jacob, Vishwani D. Agrawal: Multiple fault detection in two-level multi-output circuits. J. Electronic Testing 3(2): 171-173 (1992)
1991
47Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Vishwani D. Agrawal: A Transitive Closure Based Algorithm for Test Generation. DAC 1991: 353-358
46no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Design and Test-The Two Sides of a Coin. ICCD 1991: 12
45no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLJoan Villoldo, Prathima Agrawal, Vishwani D. Agrawal: Stafan Algorithms for MOS Circuits. ICCD 1991: 56-59
44Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal: Estimating the Quality of Manufactured Digital Sequential Circuits. ITC 1991: 210-217
1990
43Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Kwang-Ting Cheng: Test Function Specification in Synthesis. DAC 1990: 235-240
42Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKwang-Ting Cheng, Vishwani D. Agrawal: An Entropy Measure for the Complexity of Multi-Output Boolean Functions. DAC 1990: 302-305
41Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Automatic Test Generation Using Quadratic 0-1 Programming. DAC 1990: 654-659
40Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Kwang-Ting Cheng: An architecture for synthesis of testable finite state machines. EURO-DAC 1990: 612-616
39Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell: Polynomial time solvable fault detection problems. FTCS 1990: 56-63
38no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Srimat T. Chakradhar: Logic Simulation and Parallel Processing. ICCAD 1990: 496-499
37Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLDharam Vir Das, Sharad C. Seth, Paul T. Wagner, John C. Anderson, Vishwani D. Agrawal: An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited. ITC 1990: 712-720
36Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Srimat T. Chakradhar: Performance estimation in a massively parallel system. SC 1990: 306-313
35Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Hatsuyoshi Kato: Fault Sampling Revisited. IEEE Design & Test of Computers 7(4): 32-35 (1990)
34Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Vishwani D. Agrawal, Michael L. Bushnell, Thomas K. Truong: Neural Net and Boolean Satisfiability Models of Logic Circuits. IEEE Design & Test of Computers 7(5): 54-57 (1990)
33Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh: A Simulation-Based Method for Generating Tests for Sequential Circuits. IEEE Trans. Computers 39(12): 1456-1463 (1990)
32Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKwang-Ting Cheng, Vishwani D. Agrawal: A Partial Scan Method for Sequential Circuits with Feedback. IEEE Trans. Computers 39(4): 544-549 (1990)
31Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSharad C. Seth, Vishwani D. Agrawal, Hassan Farhat: A Statistical Theory of Digital Circuit Testability. IEEE Trans. Computers 39(4): 582-586 (1990)
30Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSrimat T. Chakradhar, Michael L. Bushnell, Vishwani D. Agrawal: Toward massively parallel automatic test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 9(9): 981-994 (1990)
29Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Editorial. J. Electronic Testing 1(2): 101 (1990)
28Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Kwang-Ting Cheng: Finite state machine synthesis with embedded test function. J. Electronic Testing 1(3): 221-228 (1990)
1989
27Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKwang-Ting Cheng, Vishwani D. Agrawal: An economical scan design for sequential logic test generation. FTCS 1989: 28-35
26Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPrathima Agrawal, Vishwani D. Agrawal, Kwang-Ting Cheng, R. Tutundjian: Fault Simulation in a Pipelined Multiprocessor System. ITC 1989: 727-734
25Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal: A directed search method for test generation using a concurrent simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 8(2): 131-138 (1989)
1988
24Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Kwang-Ting Cheng, Prathima Agrawal: Contest: A Concurrent Test Generator for Sequential Circuits. DAC 1988: 84-89
23Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLKwang-Ting Cheng, Vishwani D. Agrawal, Ernest S. Kuh: A sequential circuit test generation using threshold-value simulation. FTCS 1988: 24-29
1986
22no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, M. Ray Mercer: Deterministic Versus Random Testing. ITC 1986: 718
1985
21Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Samuel H. C. Poon: VLSI design process. ACM Conference on Computer Science 1985: 74-78
20Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPrathima Agrawal, Vishwani D. Agrawal, Nripendra N. Biswas: Multiple output minimization. DAC 1985: 674-680
19no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: STAFAN Takes a Middle Course. ITC 1985: 796
18Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSunil K. Jain, Vishwani D. Agrawal: Modeling and Test Generation Algorithms for MOS Circuits. IEEE Trans. Computers 34(5): 426-433 (1985)
1984
17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLAlfred E. Dunlop, Vishwani D. Agrawal, David N. Deutsch, M. F. Jukl, Patrick Kozak, Manfred Wiesel: Chip layout optimization using critical path weighting. DAC 1984: 133-136
16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSunil K. Jain, Vishwani D. Agrawal: STAFAN: An alternative to fault simulation. DAC 1984: 18-23
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSudhakar M. Reddy, Vishwani D. Agrawal, Sunil K. Jain: A gate level model for CMOS combinational logic circuits with application to fault detection. DAC 1984: 504-509
14no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Will Testability Analysis Replace Fault Simulation ? ITC 1984: 718-718
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSharad C. Seth, Vishwani D. Agrawal: Characterizing the LSI Yield Equation from Wafer Test Data. IEEE Trans. on CAD of Integrated Circuits and Systems 3(2): 123-126 (1984)
1983
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSunil K. Jain, Vishwani D. Agrawal: Test generation for MOS circuits using D-algorithm. DAC 1983: 64-70
1982
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Synchronous path analysis in MOS circuit simulator. DAC 1982: 629-635
10no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, M. Ray Mercer: Testability Measures : What Do They Tell Us ? ITC 1982: 391-399
1981
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Sharad C. Seth, Prathima Agrawal: LSI product quality and fault coverage. DAC 1981: 196-203
8no EE pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLM. Ray Mercer, Vishwani D. Agrawal, Carlos M. Roman: Test Generation for Highly Sequential Scan-Testable Circuits Through Logic Transformation. ITC 1981: 561-565
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: An Information Theoretic Approach to Digital Fault Testing. IEEE Trans. Computers 30(8): 582-587 (1981)
1980
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal, Ajoy K. Bose, Patrick Kozak, Hao N. Nham, Ernesto Pacas-Skewes: A mixed-mode simulator. DAC 1980: 618-625
1979
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Author's Reply. IEEE Trans. Computers 28(8): 581 (1979)
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: Comments on ``An Approach to Highly Integrated Computer-Maintained Cellular Arrays''. IEEE Trans. Computers 28(9): 691-693 (1979)
1978
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVishwani D. Agrawal: When to Use Random Testing. IEEE Trans. Computers 27(11): 1054-1055 (1978)
1976
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPrathima Agrawal, Vishwani D. Agrawal: On Monte Carlo Testing of Logic Tree Networks. IEEE Trans. Computers 25(6): 664-667 (1976)
1975
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPrathima Agrawal, Vishwani D. Agrawal: Probabilistic Analysis of Random Test Generation Method for Irredundant Combinational Logic Networks. IEEE Trans. Computers 24(7): 691-695 (1975)

Coauthor Index

1Prathima Agrawal [1] [2] [9] [20] [24] [25] [26] [45] [56] [58] [65] [68] [69] [71] [72] [74] [97] [101] [106] [153]
2Robert C. Aitken (Rob Aitken) [137]
3Jins D. Alexander [279]
4John C. Anderson [37]
5Jack H. Arabian [49] [85]
6Madhusudan V. Atre [204] [217]
7Dong Hyun Baik [216]
8Arun Balakrishnan [83] [87]
9Bhargab B. Bhattacharya [168] [224]
10Debashis Bhattacharya [56] [97]
11Nripendra N. Biswas [20]
12R. D. (Shawn) Blanton (Ronald D. Blanton) [122]
13Ajoy K. Bose [6]
14Soumitra Bose [58] [65] [69] [71] [107] [142] [153] [249] [250] [257] [262] [263]
15J. Braden [137]
16Michael L. Bushnell [30] [34] [39] [41] [55] [73] [78] [84] [95] [101] [102] [105] [106] [108] [117] [121] [123] [126] [129] [133] [135] [138] [147] [151] [152] [155] [156] [160] [162] [168] [170] [174] [179] [180] [203] [205] [206] [213] [214] [215] [224] [226] [227] [228] [235] [236] [237] [245] [256] [261] [268] [276]
17Tapan J. Chakraborty [55] [73] [98] [100] [104] [116] [135] [141] [179] [180]
18Srimat T. Chakradhar [30] [34] [36] [38] [39] [41] [47] [51] [54] [61] [63] [70] [78] [82] [83] [87] [92] [93] [94] [96] [134] [313]
19P. Pal Chaudhuri [109]
20Pramit Chavda [159]
21Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng) [23] [24] [25] [26] [27] [28] [32] [33] [40] [42] [43] [52] [184] [185] [187]
22Richard M. Chou [81] [136]
23Bernard Courtois [109]
24Maurizio Damiani [122]
25D. Das [64]
26Dharam Vir Das [37] [44]
27Kunal K. Dave [215] [235]
28David N. Deutsch [17]
29Suresh Kumar Devanathan [261]
30Alok S. Doshi [242]
31Alfred E. Dunlop [17]
32Kent L. Einspahr [125]
33Hassan Farhat [31]
34Joan Figueras [137]
35Vijay Gangaram [249]
36Vivek Gaur [206]
37Marwan A. Gharaybeh [105] [117] [123] [129] [151] [152] [162] [174]
38Ashish Giani [186] [192] [195] [200]
39Hillary Grimes [263]
40Michael Gustin [49]
41Keerthi Heragu [84] [95] [102] [114] [118] [124] [133] [143] [169]
42Fumiyasu Hirose [109]
43Michael S. Hsiao [186] [192] [195] [200]
44Fei Hu [240] [243] [251]
45Mahesh A. Iyer [94]
46James Jacob [48] [53] [80] [99] [103] [112] [119] [139] [159]
47Sunil K. Jain [12] [15] [16] [18]
48Wei Jiang [271] [280]
49Jing-Yang Jou [185]
50M. F. Jukl [17]
51Suman Kanjilal [54] [61] [70] [82] [93] [96]
52Kalyana R. Kantipudi [258]
53Hatsuyoshi Kato [35]
54Omar I. Khan [261]
55Kyungseok Kim [295] [304] [305]
56Yong Chang Kim [172] [193] [194] [202] [216] [234]
57Charles R. Kime [66] [67]
58Patrick Kozak [6] [17]
59Ernest S. Kuh [23] [33]
60P. R. Suresh Kumar [80]
61S. Kumar [137]
62Sandip Kundu [109]
63Erik Larsson [281]
64Chung-Len Lee [109]
65David Lee [120]
66Karen Lentz [49]
67Qing Lin [126]
68Yuanlin Lu [238] [244] [260] [269]
69Ananta K. Majhi [103] [119] [157] [158]
70Subhashis Majumder [155] [156] [168] [224]
71Vishal J. Mehta [215]
72Sreekumar Menon [277]
73M. Ray Mercer [8] [10] [22]
74Yinghua Min [109]
75Pier Luca Montessoro [49]
76Anand S. Mudlapur [239]
77Hao N. Nham [6]
78Ernesto Pacas-Skewes [6]
79Lakshminarayana Pappu [121] [147]
80Carlos G. Parodi [160] [174]
81Ganapathy Parthasarathy [170]
82Janak H. Patel [114] [118] [124] [133] [143] [169]
83Lalit M. Patnaik [103] [119]
84Samuel H. C. Poon [21]
85A. V. S. S. Prasad [204] [217]
86Tezaswi Raja [213] [226] [227] [236] [237] [245] [276]
87Rajesh Ramadoss [170]
88Lan Rao [214] [256]
89Sudhakar M. Reddy [15]
90Carlos M. Roman [8]
91Steven G. Rothweiler [63] [134]
92Kewal K. Saluja [66] [67] [81] [136] [172] [193] [194] [202] [216] [234]
93Raja K. K. R. Sandireddy [241]
94Aditya D. Sathe [205]
95Sharad C. Seth [9] [13] [31] [37] [44] [64] [68] [125] [161]
96Rajamani Sethuram [268]
97Priyadharshini Shanmugasundaram [303] [311]
98Shuo Sheng [186] [192] [195] [200]
99Mohammed Ashfaq Shukoor [282] [308]
100James Sienicki [101] [106]
101Suraj Sindia [283] [284] [291] [302] [307]
102Adit D. Singh [239] [277]
103Virendra Singh [281] [283] [284] [291] [302] [307]
104P. Srinivas Sivakumar [139]
105José T. de Sousa [183]
106Mandyam-Komar Srinivas [53] [80] [99] [108] [112] [121] [138] [147]
107Thomas G. Szymanski [142]
108Pradip A. Thaker [167] [182] [212]
109Thomas K. Truong [34]
110Huan-Chih Tsai [187]
111Jaynarayan T. Tudu [281]
112R. Tutundjian [26]
113Ernst G. Ulrich [49] [85]
114Joan Villoldo [45] [72] [74]
115Paul T. Wagner [37]
116Fan Wang [270] [278] [293]
117Li-C. Wang [185]
118Manfred Wiesel [17]
119Chi-Feng Wu [185]
120Shianling Wu [160] [185]
121Hans-Joachim Wunderlich [137]
122Nitin Yogi [259] [290]
123Mona E. Zaghloul [167] [182] [212]
124Junwu Zhang [228]
125Yu Zhang [292] [294] [306]
126Yervant Zorian [137]

Colors in the list of coauthors

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