 | 2009 |
|---|
| 5 |       | Vineet Agarwal,
Jin Sun,
Janet Meiling Wang:
Delay Uncertainty Reduction by Gate Splitting.
IEEE Trans. on Circuits and Systems 56-II(4): 295-299 (2009) |
| 2007 |
|---|
| 4 | | Vineet Agarwal,
Jin Sun,
Alexander V. Mitev,
Janet Meiling Wang:
Delay Uncertainty Reduction by Interconnect and Gate Splitting.
ASP-DAC 2007: 690-695 |
| 2006 |
|---|
| 3 | | Vineet Agarwal,
Janet Meiling Wang:
Yield-area optimizations of digital circuits using non-dominated sorting genetic algorithm (YOGA).
ASP-DAC 2006: 718-723 |
| 2 | | Navneeth Kankani,
Vineet Agarwal,
Janet Meiling Wang:
A probabilistic analysis of pipelined global interconnect under process variations.
ASP-DAC 2006: 724-729 |
| 2005 |
|---|
| 1 | | Vineet Agarwal,
Navneeth Kankani,
Ravishankar Rao,
Sarvesh Bhardwaj,
Janet Meiling Wang:
An efficient combinationality check technique for the synthesis of cyclic combinational circuits.
ASP-DAC 2005: 212-215 |
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