Kanak Agarwal

	2012
50		Vivek Joshi, Kanak Agarwal, Dennis Sylvester: Design-patterning co-optimization of SRAM robustness for double patterning lithography. ASP-DAC 2012: 713-718
	2011
49		Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal: Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect. DAC 2011: 534-539
48		Charles Lamech, Jim Aarestad, Jim Plusquellic, Reza M. Rad, Kanak Agarwal: REBEL and TDC: Two embedded test structures for on-chip measurements of within-die path delay variations. ICCAD 2011: 170-177
47		Rouwaida Kanj, Tong Li, Rajiv V. Joshi, Kanak Agarwal, Ali Sadigh, David Winston, Sani R. Nassif: Accelerated statistical simulation via on-demand Hermite spline interpolations. ICCAD 2011: 353-360
46		Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal: Measuring within-die spatial variation profile through power supply current measurements. ISQED 2011: 711-715
	2010
45		Kanak Agarwal: On-die sensors for measuring process and environmental variations in integrated circuits. ACM Great Lakes Symposium on VLSI 2010: 147-150
44		Vivek Joshi, Kanak Agarwal, Dennis Sylvester, David Blaauw: Analyzing electrical effects of RTA-driven local anneal temperature variation. ASP-DAC 2010: 739-744
43		Kanak Agarwal: Frequency domain decomposition of layouts for double dipole lithography. DAC 2010: 404-407
42		Vivek Joshi, Valeriy Sukharev, Andres Torres, Kanak Agarwal, Dennis Sylvester, David Blaauw: Closed-form modeling of layout-dependent mechanical stress. DAC 2010: 673-678
41		Vivek Joshi, Kanak Agarwal, David Blaauw, Dennis Sylvester: Analysis and optimization of SRAM robustness for double patterning lithography. ICCAD 2010: 25-31
40		Cheng Zhuo, Kanak Agarwal, David Blaauw, Dennis Sylvester: Active learning framework for post-silicon variation extraction and test cost reduction. ICCAD 2010: 508-515
39		Vivek Joshi, Kanak Agarwal, Dennis Sylvester: Simultaneous extraction of effective gate length and low-field mobility in non-uniform devices. ISQED 2010: 158-162
38		Dhruva Acharyya, Kanak Agarwal, Jim Plusquellic: Leveraging existing power control circuits and power delivery architecture for variability measurement. ITC 2010: 645-653
37		Harmander Singh, Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown: Dynamically Pulsed MTCMOS With Bus Encoding for Reduction of Total Power and Crosstalk Noise. IEEE Trans. VLSI Syst. 18(1): 166-170 (2010)
36		Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Mechanical Stress Aware Optimization for Leakage Power Reduction. IEEE Trans. on CAD of Integrated Circuits and Systems 29(5): 722-736 (2010)
	2009
35		Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic: Characterizing within-die variation from multiple supply port IDDQ measurements. ICCAD 2009: 418-424
34		Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi: The impact of BEOL lithography effects on the SRAM cell performance and yield. ISQED 2009: 607-612
	2008
33		Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Leakage power reduction using stress-enhanced layouts. DAC 2008: 912-917
32		Vivek Joshi, Brian Cline, Dennis Sylvester, David Blaauw, Kanak Agarwal: Stress aware layout optimization. ISPD 2008: 168-174
31		Victoria Wang, Kanak Agarwal, Sani R. Nassif, Kevin J. Nowka, Dejan Markovic: A Design Model for Random Process Variability. ISQED 2008: 734-737
30		Kanak Agarwal, Sani R. Nassif: The Impact of Random Device Variation on SRAM Cell Stability in Sub-90-nm CMOS Technologies. IEEE Trans. VLSI Syst. 16(1): 86-97 (2008)
29		Dennis Sylvester, Kanak Agarwal, Saumil Shah: Variability in nanometer CMOS: Impact, analysis, and minimization. Integration 41(3): 319-339 (2008)
	2007
28		Kanak Agarwal, Sani R. Nassif: Characterizing Process Variation in Nanometer CMOS. DAC 2007: 396-399
27		Kanak Agarwal, Frank Liu: Efficient computation of current flow in signal wires for reliability analysis. ICCAD 2007: 741-746
26		Kanak Agarwal, Kevin J. Nowka: Dynamic Power Management by Combination of Dual Static Supply Voltages. ISQED 2007: 85-92
25		Harmander Singh, Kanak Agarwal, Dennis Sylvester, Kevin J. Nowka: Enhanced Leakage Reduction Techniques Using Intermediate Strength Power Gating. IEEE Trans. VLSI Syst. 15(11): 1215-1224 (2007)
24		Kanak Agarwal, Rahul M. Rao, Dennis Sylvester, Richard B. Brown: Parametric Yield Analysis and Optimization in Leakage Dominated Technologies. IEEE Trans. VLSI Syst. 15(6): 613-623 (2007)
	2006
23		Kanak Agarwal, Sani R. Nassif: Statistical analysis of SRAM cell stability. DAC 2006: 57-62
22		Emrah Acar, Kanak Agarwal, Sani R. Nassif: Characterization of total chip leakage using inverse (reciprocal) gamma distribution. ISCAS 2006
21		Sani R. Nassif, Kanak Agarwal, Emrah Acar: Methods for estimating decoupling capacitance of nonswitching circuit blocks. ISCAS 2006
20		Kanak Agarwal, Kevin J. Nowka, Harmander Deogun, Dennis Sylvester: Power Gating with Multiple Sleep Modes. ISQED 2006: 633-637
19		Kanak Agarwal, Dennis Sylvester, David Blaauw: Modeling and analysis of crosstalk noise in coupled RLC interconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 25(5): 892-901 (2006)
18		Kanak Agarwal, Mridul Agarwal, Dennis Sylvester, David Blaauw: Statistical interconnect metrics for physical-design optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1273-1288 (2006)
	2005
17		Kanak Agarwal, Dennis Sylvester, David Blaauw, Anirudh Devgan: Achieving continuous VT performance in a dual VT process. ASP-DAC 2005: 393-398
16		Mridul Agarwal, Kanak Agarwal, Dennis Sylvester, David Blaauw: Statistical modeling of cross-coupling effects in VLSI interconnects. ASP-DAC 2005: 503-506
15		Ashish Srivastava, Saumil Shah, Kanak Agarwal, Dennis Sylvester, David Blaauw, Stephen W. Director: Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. DAC 2005: 535-540
14		Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Himanshu Kaul, Richard B. Brown, Sani R. Nassif: Power-aware global signaling strategies. ISCAS (1) 2005: 604-607
13		Rahul M. Rao, Kanak Agarwal, Anirudh Devgan, Kevin J. Nowka, Dennis Sylvester, Richard B. Brown: Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. ISQED 2005: 284-290
	2004
12		Kanak Agarwal, Dennis Sylvester, David Blaauw: A simplified transmission-line based crosstalk noise model for on-chip RLC wiring. ASP-DAC 2004: 858-864
11		Kanak Agarwal, Dennis Sylvester, David Blaauw, Frank Liu, Sani R. Nassif, Sarma B. K. Vrudhula: Variational delay metrics for interconnect timing analysis. DAC 2004: 381-384
10		Saumil Shah, Kanak Agarwal, Dennis Sylvester: A New Threshold Voltage Assignment Scheme for Runtime Leakage Reduction in On-Chip Repeaters. ICCD 2004: 138-143
9		Rahul M. Rao, Kanak Agarwal, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka, Sani R. Nassif: Approaches to run-time and standby mode leakage reduction in global buses. ISLPED 2004: 188-193
8		Kanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driver output model for on-chip RLC transmission lines. IEEE Trans. on CAD of Integrated Circuits and Systems 23(1): 128-136 (2004)
7		Kanak Agarwal, Dennis Sylvester, David Blaauw: A simple metric for slew rate of RC circuits based on two circuit moments. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1346-1354 (2004)
	2003
6		Kanak Agarwal, Dennis Sylvester, David Blaauw: An effective capacitance based driver output model for on-chip RLC interconnects. DAC 2003: 376-381
5		Kanak Agarwal, Dennis Sylvester, David Blaauw: Simple metrics for slew rate of RC circuits based on two circuit moments. DAC 2003: 950-953
4		Shidhartha Das, Kanak Agarwal, David Blaauw, Dennis Sylvester: Optimal Inductance for On-chip RLC Interconnections. ICCD 2003: 264-
3		Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu: Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 560-572 (2003)
	2002
2		Kanak Agarwal, Dennis Sylvester, David Blaauw: A library compatible driving point model for on-chip RLC interconnects. Timing Issues in the Specification and Synthesis of Digital Systems 2002: 63-69
1		Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu: Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. VLSI Design 2002: 77-

Coauthor Index

1	Jim Aarestad	[48] [49]
2	Emrah Acar	[21] [22]
3	Dhruva Acharyya	[35] [38] [46] [49]
4	Mridul Agarwal	[16] [18]
5	David Blaauw (David T. Blaauw)	[2] [4] [5] [6] [7] [8] [11] [12] [15] [16] [17] [18] [19] [32] [33] [36] [40] [41] [42] [44]
6	Richard B. Brown	[9] [13] [14] [24] [37]
7	Yu Cao	[1] [3]
8	Brian Cline	[32] [33] [36]
9	Shidhartha Das	[4]
10	Harmander Deogun	[20]
11	Anirudh Devgan	[13] [17]
12	Stephen W. Director	[15]
13	Chenming Hu	[1] [3]
14	Rajiv V. Joshi	[34] [47]
15	Vivek Joshi	[32] [33] [36] [39] [41] [42] [44] [50]
16	Rouwaida Kanj	[34] [47]
17	Himanshu Kaul	[14]
18	Charles Lamech	[48] [49]
19	Tong Li	[47]
20	Zhuo Li	[34]
21	Frank Liu	[11] [27]
22	Dejan Markovic	[31]
23	Sani R. Nassif	[9] [11] [14] [21] [22] [23] [28] [30] [31] [34] [47]
24	Kevin J. Nowka	[9] [13] [20] [25] [26] [31]
25	James F. Plusquellic (Jim Plusquellic)	[35] [38] [46] [48] [49]
26	Reza M. Rad	[48]
27	Rahul M. Rao	[9] [13] [14] [24] [37]
28	Ali Sadigh	[47]
29	Takashi Sato	[1] [3]
30	Saumil Shah	[10] [15] [29]
31	Weiping Shi	[34]
32	Harmander Singh	[25] [37]
33	Ashish Srivastava	[15]
34	Valeriy Sukharev	[42]
35	Dennis Sylvester	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [20] [24] [25] [29] [32] [33] [36] [37] [39] [40] [41] [42] [44] [50]
36	Andres Torres	[42]
37	Sarma B. K. Vrudhula	[11]
38	Victoria Wang	[31]
39	David Winston	[47]
40	Ying Zhou	[34]
41	Cheng Zhuo	[40]

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