Michael Adler

	2012
7		Kermin Elliott Fleming, Michael Adler, Michael Pellauer, Angshuman Parashar, Arvind, Joel S. Emer: Leveraging latency-insensitivity to ease multiple FPGA design. FPGA 2012: 175-184
	2011
6		Michael Adler, Kermin Fleming, Angshuman Parashar, Michael Pellauer, Joel S. Emer: Leap scratchpads: automatic memory and cache management for reconfigurable logic. FPGA 2011: 25-28
5		Michael Pellauer, Michael Adler, Michel A. Kinsy, Angshuman Parashar, Joel S. Emer: HAsim: FPGA-based high-detail multicore simulation using time-division multiplexing. HPCA 2011: 406-417
	2009
4		Michael Pellauer, Michael Adler, Derek Chiou, Joel S. Emer: Soft connections: addressing the hardware-design modularity problem. DAC 2009: 276-281
3		Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: A-Port Networks: Preserving the Timed Behavior of Synchronous Systems for Modeling on FPGAs. TRETS 2(3): (2009)
	2008
2		Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: A-Ports: an efficient abstraction for cycle-accurate performance models on FPGAs. FPGA 2008: 87-96
1		Michael Pellauer, Muralidaran Vijayaraghavan, Michael Adler, Arvind, Joel S. Emer: Quick Performance Models Quickly: Closely-Coupled Partitioned Simulation on FPGAs. ISPASS 2008: 1-10

Coauthor Index

1	Arvind	[1] [2] [3] [7]
2	Derek Chiou	[4]
3	Joel S. Emer	[1] [2] [3] [4] [5] [6] [7]
4	Kermin Fleming (Kermin Elliott Fleming)	[6] [7]
5	Michel A. Kinsy	[5]
6	Angshuman Parashar	[5] [6] [7]
7	Michael Pellauer	[1] [2] [3] [4] [5] [6] [7]
8	Muralidaran Vijayaraghavan	[1] [2] [3]

Last update Sat May 26 04:23:17 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page