Dhruva Acharyya

	2011
13		Jim Aarestad, Charles Lamech, Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal: Characterizing within-die and die-to-die delay variations introduced by process variations and SOI history effect. DAC 2011: 534-539
12		Jim Plusquellic, Dhruva Acharyya, Kanak Agarwal: Measuring within-die spatial variation profile through power supply current measurements. ISQED 2011: 711-715
11		Dhruva Acharyya, Kosuke Miyao, David Ting, Daniel Lam, Robert Smith, Pete Fitzpatrick, Brian Buras, John Williamson: Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current. ITC 2011: 1-10
	2010
10		Ryan Helinski, Dhruva Acharyya, Jim Plusquellic: Quality metric evaluation of a physical unclonable function derived from an IC's power distribution system. DAC 2010: 240-243
9		Dhruva Acharyya, Kanak Agarwal, Jim Plusquellic: Leveraging existing power control circuits and power delivery architecture for variability measurement. ITC 2010: 645-653
8		Jim Aarestad, Dhruva Acharyya, Reza M. Rad, Jim Plusquellic: Detecting Trojans Through Leakage Current Analysis Using Multiple Supply Pad IDDQ s. IEEE Transactions on Information Forensics and Security 5(4): 893-904 (2010)
	2009
7		Ryan Helinski, Dhruva Acharyya, Jim Plusquellic: A physical unclonable function defined using power distribution system equivalent resistance variations. DAC 2009: 676-681
6		Kanak Agarwal, Dhruva Acharyya, Jim Plusquellic: Characterizing within-die variation from multiple supply port IDDQ measurements. ICCAD 2009: 418-424
	2007
5		Rouwaida Kanj, Rajiv V. Joshi, Jayakumaran Sivagnaname, Jente B. Kuang, Dhruva Acharyya, Tuyet Nguyen, Chandler McDowell, Sani R. Nassif: Gate Leakage Effects on Yield and Design Considerations of PD/SOI SRAM Designs. ISQED 2007: 33-40
	2006
4		Jim Plusquellic, Dhruva Acharyya, Abhishek Singh, Mohammad Tehranipoor, Chintan Patel: Quiescent-Signal Analysis: A Multiple Supply Pad IDDQ Method. IEEE Design & Test of Computers 23(4): 278-293 (2006)
	2005
3		Dhruva Acharyya, Jim Plusquellic: Hardware Results Demonstrating Defect Detection Using Power Supply Signal Measurements. VTS 2005: 433-438
	2003
2		Dhruva Acharyya, Jim Plusquellic: Impedance Profile of a Commercial Power Grid and Test System. ITC 2003: 709-718
1		Chintan Patel, Ernesto Staroswiecki, Smita Pawar, Dhruva Acharyya, Jim Plusquellic: Defect Diagnosis Using a Current Ratio Based Quiescent Signal Analysis Model for Commercial Power Grids. J. Electronic Testing 19(6): 611-623 (2003)

Coauthor Index

1	Jim Aarestad	[8] [13]
2	Kanak Agarwal	[6] [9] [12] [13]
3	Brian Buras	[11]
4	Pete Fitzpatrick	[11]
5	Ryan Helinski	[7] [10]
6	Rajiv V. Joshi	[5]
7	Rouwaida Kanj	[5]
8	Jente B. Kuang	[5]
9	Daniel Lam	[11]
10	Charles Lamech	[13]
11	Chandler McDowell	[5]
12	Kosuke Miyao	[11]
13	Sani R. Nassif	[5]
14	Tuyet Nguyen	[5]
15	Chintan Patel	[1] [4]
16	Smita Pawar	[1]
17	James F. Plusquellic (Jim Plusquellic)	[1] [2] [3] [4] [6] [7] [8] [9] [10] [12] [13]
18	Reza M. Rad	[8]
19	Abhishek Singh	[4]
20	Jayakumaran Sivagnaname	[5]
21	Robert Smith	[11]
22	Ernesto Staroswiecki	[1]
23	Mohammad Tehranipoor	[4]
24	David Ting	[11]
25	John Williamson	[11]

Colors in the list of coauthors

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