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| 1995 | ||
|---|---|---|
| 1 | I. S. Abu-Khater, A. Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan: Circuit/architecture for low-power high-performance 32-bit adder. Great Lakes Symposium on VLSI 1995: 74- | |
| 1 | A. Bellaouar | [1] |
| 2 | Mohamed I. Elmasry | [1] |
| 3 | Ran-Hong Yan | [1] |
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