Ben A. Abderazek

Ben Abdallah Abderazek

	2011
30		Ben Abdallah Abderazek, Masashi Masuda, Arquimedes Canedo, Kenichi Kuroda: Natural instruction level parallelism-aware compiler for high-performance QueueCore processor architecture. The Journal of Supercomputing 57(3): 314-338 (2011)
	2010
29		Akram Ben Ahmed, Ben Abdallah Abderazek, Kenichi Kuroda: Architecture and Design of Efficient 3D Network-on-Chip (3D NoC) for Custom Multicore SoC. BWCCA 2010: 67-73
28		Kenichi Mori, Adam Esch, Ben Abdallah Abderazek, Kenichi Kuroda: Advanced Design Issues for OASIS Network-on-Chip Architecture. BWCCA 2010: 74-79
27		Ben Abdallah Abderazek, Yasuyoshi Haga, Kenichi Kuroda: An Efficient Algorithm and Embedded Multicore Implementation of ECG Analysis in Multi-lead Electrocardiogram Records. ICPP Workshops 2010: 99-103
26		Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: Compiling for Reduced Bit-Width Queue Processors. Signal Processing Systems 59(1): 45-55 (2010)
	2009
25		Masashi Masuda, Ben Abdallah Abderazek, Arquimedes Canedo: Software and Hardware Design Issues for Low Complexity High Performance Processor Architecture. ICPP Workshops 2009: 558-565
24		Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: Design and implementation of a queue compiler. Microprocessors and Microsystems - Embedded Hardware Design 33(2): 129-138 (2009)
23		Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: Efficient compilation for queue size constrained queue processors. Parallel Computing 35(4): 213-225 (2009)
22		Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: Compiler Support for Code Size Reduction Using a Queue-Based Processor. T. HiPEAC 2: 269-285 (2009)
	2008
21		Hiroki Hoshino, Ben A. Abderazek, Kenichi Kuroda: Advanced Optimization and Design Issues of a 32-Bit Embedded Processor Based on Produced Order Queue Computation Model. EUC (1) 2008: 16-22
20		Taichi Maekawa, Ben A. Abderazek, Kenichi Kuroda: Single Instruction Dual-Execution Model Processor Architecture. EUC (1) 2008: 30-36
19		Arquimedes Canedo, Masahiro Sowa, Ben A. Abderazek: Quantitative Evaluation of Common Subexpression Elimination on Queue Machines. ISPAN 2008: 25-30
18		Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: A new code generation algorithm for 2-offset producer order queue computation model. Computer Languages, Systems & Structures 34(4): 184-194 (2008)
17		Ben A. Abderazek, Arquimedes Canedo, Tsutomu Yoshinaga, Masahiro Sowa: The QC-2 parallel Queue processor architecture. J. Parallel Distrib. Comput. 68(2): 235-245 (2008)
16		Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa: Dual-execution mode processor architecture. The Journal of Supercomputing 44(2): 103-125 (2008)
	2007
15		Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: An Efficient Code Generation Algorithm for Code Size Reduction Using 1-Offset P-Code Queue Computation Model. EUC 2007: 196-208
14		Ben A. Abderazek, Mushfiquzzaman Akanda, Tsutomu Yoshinaga, Masahiro Sowa: Mathematical Model for Multiobjective Synthesis of NoC Architectures. ICPP Workshops 2007: 36
13		Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: New Code Generation Algorithm for QueueCore—An Embedded Processor with High ILP. PDCAT 2007: 185-192
12		Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: Queue Register File Optimization Algorithm for QueueCore Processor. SBAC-PAD 2007: 169-176
11		Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa: Dual-Execution Mode Processor Architecture For Embedded Applications. J. Mobile Multimedia 3(4): 347-370 (2007)
10		Yuki Nakanishi, Arquimedes Canedo, Ben A. Abderazek, Masahiro Sowa: Optimizing Reaching Definitions Overhead in Queue Processors. JCIT 2(4): 36-40 (2007)
	2006
9		Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa: Scalable Core-Based Methodology and Synthesizable Core for Systematic Design. ICPP Workshops 2006: 345-352
8		Md. Musfiquzzaman Akanda, Ben A. Abderazek, Masahiro Sowa: On the Design of a Dual-Execution Modes Processor: Architecture and Preliminary Evaluation. ISPA Workshops 2006: 37-46
7		Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa: Design and architecture for an embedded 32-bit QueueCore. J. Embedded Computing 2(2): 191-205 (2006)
6		Ben A. Abderazek, Tsutomu Yoshinaga, Masahiro Sowa: High-Level Modeling and FPGA Prototyping of Produced Order Parallel Queue Processor Core. The Journal of Supercomputing 38(1): 3-15 (2006)
	2005
5		Ben A. Abderazek, Sotaro Kawata, Tsutomu Yoshinaga, Masahiro Sowa: Modular Design Structure and High-Level Prototyping for Novel Embedded Processor Core. EUC 2005: 340-349
4		Md. Musfiquzzaman Akanda, Ben A. Abderazek, Sotaro Kawata, Masahiro Sowa: An Efficient Dynamic Switching Mechanism (DSM) for Hybrid Processor Architecture. EUC 2005: 77-86
3		Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga: Parallel Queue Processor Architecture Based on Produced Order Computation Model. The Journal of Supercomputing 32(3): 217-229 (2005)
	2003
2		Ben A. Abderazek, Soichi Shigeta, Tsutomu Yoshinaga, Masahiro Sowa: On the Design of a Register Queue Based Processor Architecture (FaRM-rq). ISPA 2003: 248-262
	2002
1		Masahiro Sowa, Ben A. Abderazek, Soichi Shigeta, Kirilka Nikolova, Tsutomu Yoshinaga: Proposal and Design of a Parallel Queue Processor Architecture (PQP). IASTED PDCS 2002: 549-554

Coauthor Index

1	Akram Ben Ahmed	[29]
2	Md. Musfiquzzaman Akanda	[4] [8] [11] [16]
3	Mushfiquzzaman Akanda	[14]
4	Arquimedes Canedo	[10] [12] [13] [15] [17] [18] [19] [22] [23] [24] [25] [26] [30]
5	Adam Esch	[28]
6	Yasuyoshi Haga	[27]
7	Hiroki Hoshino	[21]
8	Sotaro Kawata	[4] [5] [7]
9	Kenichi Kuroda	[20] [21] [27] [28] [29] [30]
10	Taichi Maekawa	[20]
11	Masashi Masuda	[25] [30]
12	Kenichi Mori	[28]
13	Yuki Nakanishi	[10]
14	Kirilka Nikolova	[1]
15	Soichi Shigeta	[1] [2]
16	Masahiro Sowa	[1] [2] [3] [4] [5] [6] [7] [8] [9] [10] [11] [12] [13] [14] [15] [16] [17] [18] [19] [22] [23] [24] [26]
17	Tsutomu Yoshinaga	[1] [2] [3] [5] [6] [9] [14] [17]

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