Magdy S. Abadir

	2011
123		Magdy S. Abadir, Jay Bhadra, Li-C. Wang: 12th International Workshop on Microprocessor Test and Verification, MTV 2011, Austin, TX, USA, December 5-7, 2011 IEEE 2011
122		Dragoljub Gagi Drmanac, Nik Sumikawa, LeRoy Winemberg, Li-C. Wang, Magdy S. Abadir: Multidimensional parametric test set optimization of wafer probe data for predicting in field failures and setting tighter test limits. DATE 2011: 794-799
121		Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir: Forward prediction based on wafer sort data - A case study. ITC 2011: 1-10
120		Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir: Understanding customer returns from a test perspective. VTS 2011: 2-7
	2010
119		Magdy S. Abadir, Jay Bhadra, Li-C. Wang: 11th International Workshop on Microprocessor Test and Verification, MTV 2010, Austin, TX, USA, December 13-15, 2010 IEEE 2010
118		Nicholas Callegari, Dragoljub Gagi Drmanac, Li-C. Wang, Magdy S. Abadir: Classification rule learning using subgroup discovery of cross-domain attributes responsible for design-silicon mismatch. DAC 2010: 374-379
117		Alper Sen, Magdy S. Abadir: Coverage metrics for verification of concurrent SystemC designs using mutation testing. HLDVT 2010: 75-81
116		Magdy S. Abadir: Design for reality: knowledge discovery in design and test data. SBCCI 2010: 54
115		Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir: Feature-Ranking Methodology to Diagnose Design-Silicon Timing Mismatch. IEEE Design & Test of Computers 27(3): 42-53 (2010)
	2009
114		Amin Khajeh, Aseem Gupta, Nikil Dutt, Fadi J. Kurdahi, Ahmed M. Eltawil, Kamal S. Khouri, Magdy S. Abadir: TRAM: A tool for Temperature and Reliability Aware Memory Design. DATE 2009: 340-345
113		Dragoljub Gagi Drmanac, Brendon Bolin, Li-C. Wang, Magdy S. Abadir: Minimizing outlier delay test cost in the presence of systematic variability. ITC 2009: 1-10
112		Nicholas Callegari, Pouria Bastani, Li-C. Wang, Magdy S. Abadir: A Statistical Diagnosis Approach for Analyzing Design-Silicon Timing Mismatch. IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1728-1741 (2009)
	2008
111		Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir: Statistical diagnosis of unmodeled systematic timing effects. DAC 2008: 355-360
110		Alper Sen, Vinit Ogale, Magdy S. Abadir: Predictive runtime verification of multi-processor SoCs in SystemC. DAC 2008: 948-953
109		Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: Thermal Aware Global Routing of VLSI Chips for Enhanced Reliability. ISQED 2008: 470-475
108		Pouria Bastani, Nicholas Callegari, Li-C. Wang, Magdy S. Abadir: Diagnosis of design-silicon timing mismatch with feature encoding and importance ranking - the methodology explained. ITC 2008: 1-10
107		Pouria Bastani, Li-C. Wang, Magdy S. Abadir: Linking Statistical Learning to Diagnosis. IEEE Design & Test of Computers 25(3): 232-239 (2008)
106		Jayanta Bhadra, Ekaterina Trofimova, Magdy S. Abadir: Validating Power ArchitectureTM Technology-Based MPSoCs Through Executable Specifications. IEEE Trans. VLSI Syst. 16(4): 388-396 (2008)
	2007
105		Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra: Eighth International Workshop on Microprocessor Test and Verification (MTV 2007), Common Challenges and Solutions, 5-6 December 2007, Austin, Texas, USA IEEE Computer Society 2007
104		Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: LEAF: A System Level Leakage-Aware Floorplanner for SoCs. ASP-DAC 2007: 274-279
103		Li-C. Wang, Pouria Bastani, Magdy S. Abadir: Design-Silicon Timing Correlation A Data Mining Perspective. DAC 2007: 384-389
102		Hratch Mangassarian, Andreas G. Veneris, Sean Safarpour, Farid N. Najm, Magdy S. Abadir: Maximum circuit activity estimation using pseudo-boolean satisfiability. DATE 2007: 1538-1543
101		Pouria Bastani, Benjamin N. Lee, Li-C. Wang, Savithri Sundareswaran, Magdy S. Abadir: Analyzing the risk of timing modeling based on path delay tests. ITC 2007: 1-10
100		Sean Hsi Yuan Wu, Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir: Statistical analysis and optimization of parametric delay test. ITC 2007: 1-10
99		Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. VLSI Design 2007: 559-564
98		Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang: Guest Editors' Introduction: Attacking Functional Verification through Hybrid Techniques. IEEE Design & Test of Computers 24(2): 110-111 (2007)
97		Jayanta Bhadra, Magdy S. Abadir, Li-C. Wang, Sandip Ray: A Survey of Hybrid Techniques for Functional Verification. IEEE Design & Test of Computers 24(2): 112-122 (2007)
	2006
96		Magdy S. Abadir, Li-C. Wang, Jayanta Bhadra: Seventh International Workshop on Microprocessor Test and Verification (MTV 2006), Common Challenges and Solutions, 4-5 December 2006, Austin, Texas, USA IEEE Computer Society 2006
95		Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir: Floorplan driven leakage power aware IP-based SoC design space exploration. CODES+ISSS 2006: 118-123
94		Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir: Refined statistical static timing analysis through. DAC 2006: 149-154
93		Onur Guzey, Charles H.-P. Wen, Li-C. Wang, Tao Feng, Hillel Miller, Magdy S. Abadir: Extracting a Simplified View of Design Functionality Based on Vector Simulation. Haifa Verification Conference 2006: 34-49
92		Magdy S. Abadir: Floorplanning and Thermal Impact on Leakage Power and Proper Operation of Complex SOC Designs. IOLTS 2006: 81
91		Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir: Issues on Test Optimization with Known Good Dies and Known Defective Dies - A Statistical Perspective. ITC 2006: 1-10
90		Heon-Mo Koo, Prabhat Mishra, Jayanta Bhadra, Magdy S. Abadir: Directed Micro-architectural Test Generation for an Industrial Processor: A Case Study. MTV 2006: 33-36
	2005
89		Magdy S. Abadir, Li-C. Wang: Sixth International Workshop on Microprocessor Test and Verification (MTV 2005), Common Challenges and Solutions, 3-4 November 2005, Austin, Texas, USA IEEE Computer Society 2005
88		Jiang Brandon Liu, Magdy S. Abadir, Andreas G. Veneris, Sean Safarpour: Diagnosing multiple transition faults in the absence of timing information. ACM Great Lakes Symposium on VLSI 2005: 193-196
87		Dennis Wassung, Yervant Zorian, Magdy S. Abadir, Mark Bapst, Colin Harris: Choosing flows and methodologies for SoC design. DAC 2005: 167
86		Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-verification debugging of hierarchical designs. ICCAD 2005: 871-876
85		Benjamin N. Lee, Hui Li, Li-C. Wang, Magdy S. Abadir: Hazard-aware statistical timing simulation and its applications in screening frequency-dependent defects. ITC 2005: 10
84		Jayanta Bhadra, Magdy S. Abadir, David Burgess, Ekaterina Trofimova: Automatic Generation of High Performance Embedded Memory Models for PowerPC Microprocessors. MTV 2005: 111-118
83		Brian Kahne, Magdy S. Abadir: Retiming Verification Using Sequential Equivalence Checking. MTV 2005: 138-142
82		Moayad Fahim Ali, Sean Safarpour, Andreas G. Veneris, Magdy S. Abadir, Rolf Drechsler: Post-Verification Debugging of Hierarchical Designs. MTV 2005: 42-47
81		Dhiraj K. Pradhan, Magdy S. Abadir, Mauricio Varea: Recent Advances in Verification, Equivalence Checking and SAT-Solvers. VLSI Design 2005: 14
80		Benjamin N. Lee, Li-C. Wang, Magdy S. Abadir: Reducing Pattern Delay Variations for Screening Frequency Dependent Defects. VTS 2005: 153-160
79		Prabhat Mishra, Nikil D. Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A methodology for validation of microprocessors using symbolic simulation. IJES 1(1/2): 14-22 (2005)
78		Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Sep Seyedi: Functional Fault Equivalence and Diagnostic Test Generation in Combinational Logic Circuits Using Conventional ATPG. J. Electronic Testing 21(5): 495-502 (2005)
	2004
77		Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir: Analytical models for leakage power estimation of memory array structures. CODES+ISSS 2004: 146-151
76		Li-C. Wang, T. M. Mak, Kwang-Ting Cheng, Magdy S. Abadir: On path-based learning and its applications in delay test and diagnosis. DAC 2004: 492-497
75		Moayad Fahim Ali, Andreas G. Veneris, Alexander Smith, Sean Safarpour, Rolf Drechsler, Magdy S. Abadir: Debugging sequential circuits using Boolean satisfiability. ICCAD 2004: 204-209
74		Andreas G. Veneris, Robert Chang, Magdy S. Abadir, Mandana Amiri: Fault equivalence and diagnostic test generation using ATPG. ISCAS (5) 2004: 221-224
73		Jing Zeng, Magdy S. Abadir, A. Kolhatkar, G. Vandling, Li-C. Wang, Jacob A. Abraham: On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. ITC 2004: 31-37
72		Jing Zeng, Magdy S. Abadir, G. Vandling, Li-C. Wang, S. Karako, Jacob A. Abraham: On Correlating Structural Tests with Functional Tests for Speed Binning of High Performance Design. MTV 2004: 103-109
71		Moayad Fahim Ali, Andreas G. Veneris, Sean Safarpour, Magdy S. Abadir, Freescale Semiconductor, Rolf Drechsler, Alexander Smith: Debugging Sequential Circuits Using Boolean Satisfiability. MTV 2004: 44-49
70		M. Moiz Khan, Spyros Tragoudas, Magdy S. Abadir, Jiang Brandon Liu: Identification of Gates for Covering all Critical Paths. MTV 2004: 92-96
69		Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Towards The Complete Elimination of Gate/Switch Level Simulations. VLSI Design 2004: 115-
68		Prabhat Mishra, Nikil Dutt, Narayanan Krishnamurthy, Magdy S. Abadir: A Top-Down Methodology for Microprocessor Validation. IEEE Design & Test of Computers 21(2): 122-131 (2004)
67		Magdy S. Abadir, Li-C. Wang: Guest Editors' Introduction: The Verification and Test of Complex Digital ICs. IEEE Design & Test of Computers 21(2): 80-82 (2004)
66		Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir: Enhanced Equivalence Checking: Toward a Solidarity of Functional Verification and Manufacturing Test Generation. IEEE Design & Test of Computers 21(6): 494-502 (2004)
65		Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir: IDAP: a tool for high-level power estimation of custom array structures. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1361-1369 (2004)
	2003
64		Magdy S. Abadir, Jing Zeng, Carol Pyron, Juhong Zhu: Automated Test Model Generation from Switch Level Custom Circuits. Asian Test Symposium 2003: 184-189
63		Angela Krstic, Li-C. Wang, Kwang-Ting Cheng, Jing-Jia Liou, Magdy S. Abadir: Delay Defect Diagnosis Based Upon Statistical Timing Models - The First Step. DATE 2003: 10328-10335
62		Mahesh Mamidipaka, Kamal S. Khouri, Nikil D. Dutt, Magdy S. Abadir: IDAP: A Tool for High Level Power Estimation of Custom Array Structures. ICCAD 2003: 113-119
61		Li-C. Wang, Angela Krstic, Leonard Lee, Kwang-Ting Cheng, M. Ray Mercer, Thomas W. Williams, Magdy S. Abadir: Using Logic Models To Predict The Detection Behavior Of Statistical Timing Defects. ITC 2003: 1041-1050
60		Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir: A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. MTV 2003: 32-37
59		Magdy S. Abadir, Juhong Zhu: Transition Test Generation using Replicate-and-Reduce Transform for Scan-based Designs. VTS 2003: 22-30
58		Li-C. Wang, Tao Feng, Kwang-Ting (Tim) Cheng, Magdy S. Abadir, Manish Pandey: Enhanced Symbolic Simulation for Functional Verification of Embedded Array Systems. Design Autom. for Emb. Sys. 8(2-3): 173-188 (2003)
57		Magdy S. Abadir, Ken Albin, John Havlicek, Narayanan Krishnamurthy, Andrew K. Martin: Formal Verification Successes at Motorola. Formal Methods in System Design 22(2): 117-123 (2003)
	2002
56		Jing Zeng, Magdy S. Abadir, Jacob A. Abraham: False timing path identification using ATPG techniques and delay-based information. DAC 2002: 562-565
55		Andreas G. Veneris, Jiang Brandon Liu, Mandana Amiri, Magdy S. Abadir: Incremental Diagnosis and Correction of Multiple Faults and Errors. DATE 2002: 716-721
54		A. J. van de Goor, Magdy S. Abadir, Alan Carlin: Minimal Test for Coupling Faults in Word-Oriented Memories. DATE 2002: 944-948
53		Ganapathy Parthasarathy, Madhu K. Iyer, Tao Feng, Li-C. Wang, Kwang-Ting Cheng, Magdy S. Abadir: Combining ATPG and Symbolic Simulation for Efficient Validation of Embedded Array Systems. ITC 2002: 203-212
52		Andreas G. Veneris, Magdy S. Abadir, Mandana Amiri: Design Rewiring Using ATPG. ITC 2002: 223-232
51		Li-C. Wang, Magdy S. Abadir, Juhong Zhu: On Testing High-Performance Custom Circuits without Explicit Testing of the Internal Faults. ITC 2002: 398-406
50		Narayanan Krishnamurthy, Jayanta Bhadra, Magdy S. Abadir, Jacob A. Abraham: Is State Mapping Essential for Equivalence Checking Custom Memories in Scan-Based Designs? VTS 2002: 275-280
49		Andreas G. Veneris, Magdy S. Abadir: Design rewiring using ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 21(12): 1469-1479 (2002)
	2001
48		Andreas G. Veneris, Magdy S. Abadir, Ivor Ting: Design rewiring based on diagnosis techniques. ASP-DAC 2001: 479-484
47		Jayanta Bhadra, Andrew K. Martin, Jacob A. Abraham, Magdy S. Abadir: Using Abstract Specifications to Verify PowerPCTM Custom Memories by Symbolic Trajectory Evaluation. CHARME 2001: 386-402
46		Jing Zeng, Magdy S. Abadir, Jayanta Bhadra, Jacob A. Abraham: Full chip false timing path identification: applications to the PowerPCTM microprocessors. DATE 2001: 514-519
45		Mrinal Bose, Elizabeth M. Rudnick, Magdy S. Abadir: Automatic Bias Generation Using Pipeline Instruction State Coverage for Biased Random Instruction Generation. IOLTW 2001: 65-
44		Magdy S. Abadir, Li-C. Wang: Verification and Validation of Complex Digital Systems: An Industrial Perspective. ISQED 2001: 11-12
43		Magdy S. Abadir, Juhong Zhu, Li-C. Wang: Analysis of Testing Methodologies for Custom Designs in PowerPCTM Microprocessor. VTS 2001: 252-259
42		Magdy S. Abadir, Scott Davidson, Vijay Nagasamy, Dhiraj K. Pradhan, Prab Varma: ATPG for Design Errors-Is It Possible? VTS 2001: 283-285
41		Narayanan Krishnamurthy, Magdy S. Abadir, Andrew K. Martin, Jacob A. Abraham: Design and Development Paradigm for Industrial Formal Verification CAD Tools. IEEE Design & Test of Computers 18(4): 26-35 (2001)
40		Jay Bedsole, Rajesh Raina, Al Crouch, Magdy S. Abadir: Very Low Cost Testers: Opportunities and Challenges. IEEE Design & Test of Computers 18(5): 60-69 (2001)
	2000
39		Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham: Validation of PowerPC(tm) Custom Memories using Symbolic Simulation. VTS 2000: 9-14
38		Magdy S. Abadir, Sumit Dasgupta: Guest Editors' Introduction: Microprocessor Test and Verification. IEEE Design & Test of Computers 17(4): 4-5 (2000)
37		Narayanan Krishnamurthy, Andrew K. Martin, Magdy S. Abadir, Jacob A. Abraham: Validating PowerPC Microprocessor Custom Memories. IEEE Design & Test of Computers 17(4): 61-76 (2000)
36		Li-C. Wang, Magdy S. Abadir: On Efficiently Producing Quality Tests for Custom Circuits in PowerPCTM Microprocessors. J. Electronic Testing 16(1-2): 121-130 (2000)
35		Wen Ching Wu, Chung-Len Lee, Ming Shae Wu, Jwu E. Chen, Magdy S. Abadir: Oscillation Ring Delay Test for High Performance Microprocessors. J. Electronic Testing 16(1-2): 147-155 (2000)
34		Magdy S. Abadir: Guest Editorial. J. Electronic Testing 16(1-2): 9-10 (2000)
	1999
33		Magdy S. Abadir, Rajesh Raina: Design-for-test methodology for Motorola PowerPC microprocessors. ITC 1999: 810-819
32		Li-C. Wang, Magdy S. Abadir: Tradeoff analysis for producing high quality tests for custom circuits in PowerPC microprocessors. ITC 1999: 830-838
31		Li-C. Wang, Magdy S. Abadir: Experience in Validation of PowerPCTM Microprocessor Embedded Arrays. J. Electronic Testing 15(1-2): 191-205 (1999)
	1998
30		Li-C. Wang, Magdy S. Abadir, Nari Krishnamurthy: Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. DAC 1998: 534-537
29		Li-C. Wang, Magdy S. Abadir, Jing Zeng: Measuring the Effectiveness of Various Design Validation Approaches For PowerPC(TM) Microprocessor Arrays. DATE 1998: 273-277
28		Arun Chandra, Li-C. Wang, Magdy S. Abadir: Practical Considerations in Formal Equivalence Checking of PowerPC(tm) Microprocessors. Great Lakes Symposium on VLSI 1998: 362-367
27		Li-C. Wang, Magdy S. Abadir, Jing Zeng: On Logic and Transistor Level Design Error Detection of Various Validation Approaches for PowerPC(tm) Microprocessor Arrays. VTS 1998: 260-265
26		Li-C. Wang, Magdy S. Abadir, Jing Zeng: On measuring the effectiveness of various design validation approaches for PowerPC microprocessor embedded arrays. ACM Trans. Design Autom. Electr. Syst. 3(4): 524-532 (1998)
25		Li-C. Wang, Magdy S. Abadir: Test Generation Based on High-Level Assertion Specification for PowerPCTM Microprocessor Embedded Arrays. J. Electronic Testing 13(2): 121-135 (1998)
	1997
24		Manish Pandey, Richard Raimi, Randal E. Bryant, Magdy S. Abadir: Formal Verification of Content Addressable Memories Using Symbolic Trajectory Evaluation. DAC 1997: 167-172
23		Li-C. Wang, Magdy S. Abadir: A New Validation Methodology Combining Test and Formal Verification for PowerPCTM Microprocessor Arrays. ITC 1997: 954-963
22		Magdy S. Abadir, Jacob A. Abraham, H. Hao, C. Hunter, Wayne M. Needham, Ron G. Walther: Microprocessor Test and Validation: Any New Avenues? VTS 1997: 458-464
21		Tony Ambler, Magdy S. Abadir: Design and Test Economics-An Extra Dimension. IEEE Design & Test of Computers 14(3): 15-16 (1997)
20		Magdy S. Abadir, Rohit Kapur: Cost-Driven Ranking of Memory Elements for Partial Intrusion. IEEE Design & Test of Computers 14(3): 45-50 (1997)
19		Jawahar Jain, James R. Bitner, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell: Indexed BDDs: Algorithmic Advances in Techniques to Represent and Verify Boolean Functions. IEEE Trans. Computers 46(11): 1230-1245 (1997)
18		Cynthia F. Murphy, Magdy S. Abadir, Peter Sandborn: Economic Analysis of Test Process Flows for Multichip Modules Using Known Good Die. J. Electronic Testing 10(1-2): 151-166 (1997)
	1996
17		Neeta Ganguly, Magdy S. Abadir, Manish Pandey: PowerPCTM Array Verification Methodology using Formal Techniques. ITC 1996: 857-864
	1994
16		James R. Bitner, Jawahar Jain, Magdy S. Abadir, Jacob A. Abraham, Donald S. Fussell: Efficient Algorithmic Circuit Verification Using Indexed BDDs. FTCS 1994: 266-275
15		Magdy S. Abadir, Ashish R. Parikh, Linda Bal, Peter Sandborn, Ken Drake: Analyzing Multichip Module Testing Strategies. IEEE Design & Test of Computers 11(1): 40-52 (1994)
14		Magdy S. Abadir, Tony Ambler: Introduction. J. Electronic Testing 5(2-3): 129-130 (1994)
13		Magdy S. Abadir, Ashish Parikh, Linda Bal, Peter Sandborn, Cynthia F. Murphy: High Level Test Economics Advisor (Hi-TEA). J. Electronic Testing 5(2-3): 195-206 (1994)
12		Peter Sandborn, Rajarshi Ghosh, Ken Drake, Magdy S. Abadir, Linda Bal, Ashish Parikh: Multichip systems trade-off analysis tool. J. Electronic Testing 5(2-3): 207-218 (1994)
	1993
11		Praveen Vishakantaiah, Thomas Thomas, Jacob A. Abraham, Magdy S. Abadir: AMBIANT: Automatic Generation of Behavioral Modifications for Testability. ICCD 1993: 63-66
	1992
10		Praveen Vishakantaiah, Jacob A. Abraham, Magdy S. Abadir: Automatic Test Knowledge Extraction from VHDL (ATKET). DAC 1992: 273-278
	1991
9		Magdy S. Abadir, Joe Newman, Desmond D'Souza, Steve Spencer: Partitioning Hierarchical Designs for Testability. ITC 1991: 174-183
	1990
8		Magdy S. Abadir, Jack Ferguson: An improved layout verification algorithm (LAVA). EURO-DAC 1990: 391-395
	1988
7		Magdy S. Abadir, Jack Ferguson, Tom E. Kirkland: Logic design verification via test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 7(1): 138-148 (1988)
	1986
6		Magdy S. Abadir, Melvin A. Breuer: Scan Path with Look Ahead Shifting (SPLASH). ITC 1986: 696-704
5		Magdy S. Abadir, Melvin A. Breuer: Test Schedules for VLSI Circuits Having Built-In Test Hardware. IEEE Trans. Computers 35(4): 361-367 (1986)
4		Magdy S. Abadir, Hassan K. Reghbati: Functional Test Generation for Digital Circuits Described Using Binary Decision Diagrams. IEEE Trans. Computers 35(4): 375-379 (1986)
	1985
3		Magdy S. Abadir, Hassan K. Reghbati: Functional Test Generation for LSI Circuits Described by Binary Decision Diagrams. ITC 1985: 483-492
	1984
2		Magdy S. Abadir, Hassan K. Reghbati: Test generation for LSI: A case study. DAC 1984: 180-195
	1983
1		Magdy S. Abadir, Hassan K. Reghbati: Functional Testing of Semiconductor Random Access Memories. ACM Comput. Surv. 15(3): 175-198 (1983)

Coauthor Index

1	Jacob A. Abraham	[10] [11] [16] [19] [22] [37] [39] [41] [46] [47] [50] [56] [69] [72] [73]
2	Ken Albin	[57]
3	Moayad Fahim Ali	[71] [75] [82] [86]
4	Tony Ambler	[14] [21]
5	Mandana Amiri	[52] [55] [74]
6	Linda Bal	[12] [13] [15]
7	Mark Bapst	[87]
8	Pouria Bastani	[101] [103] [107] [108] [111] [112] [115]
9	Jay Bedsole	[40]
10	Jayanta Bhadra (Jay Bhadra)	[46] [47] [50] [60] [66] [69] [84] [90] [96] [97] [98] [105] [106] [119] [123]
11	James R. Bitner	[16] [19]
12	Brendon Bolin	[113]
13	Mrinal Bose	[45]
14	Melvin A. Breuer	[5] [6]
15	Randal E. Bryant	[24]
16	David Burgess	[84]
17	Nicholas Callegari	[108] [111] [112] [115] [118]
18	Alan Carlin	[54]
19	Arun Chandra	[28]
20	Robert Chang	[74] [78]
21	Jwu E. Chen	[35]
22	Kwang-Ting Cheng (Kwang-Ting (Tim) Cheng)	[53] [58] [61] [63] [76]
23	Alfred L. Crouch (Al Crouch)	[40]
24	Desmond D'Souza	[9]
25	Sumit Dasgupta	[38]
26	Scott Davidson	[42]
27	Amin Khajeh Djahromi (Amin Khajeh)	[114]
28	Ken Drake	[12] [15]
29	Rolf Drechsler	[71] [75] [82] [86]
30	Dragoljub Gagi Drmanac	[113] [118] [120] [121] [122]
31	Nikil D. Dutt (Nikil Dutt)	[62] [65] [68] [77] [79] [95] [99] [104] [109] [114]
32	Ahmed M. Eltawil	[114]
33	Tao Feng	[53] [58] [93]
34	Jack Ferguson	[7] [8]
35	Donald S. Fussell	[16] [19]
36	Neeta Ganguly	[17]
37	Rajarshi Ghosh	[12]
38	A. J. van de Goor	[54]
39	Aseem Gupta	[95] [99] [104] [109] [114]
40	Onur Guzey	[93]
41	H. Hao	[22]
42	Colin Harris	[87]
43	John Havlicek	[57]
44	C. Hunter	[22]
45	Madhu K. Iyer	[53]
46	Jawahar Jain	[16] [19]
47	Brian Kahne	[83]
48	Rohit Kapur	[20]
49	S. Karako	[72]
50	M. Moiz Khan	[70]
51	Kamal S. Khouri	[62] [65] [77] [95] [99] [104] [109] [114]
52	Tom E. Kirkland	[7]
53	A. Kolhatkar	[73]
54	Heon-Mo Koo	[90]
55	Narayanan Krishnamurthy	[37] [39] [41] [50] [57] [60] [66] [68] [69] [79]
56	Nari Krishnamurthy	[30]
57	Angela Krstic	[61] [63]
58	Fadi J. Kurdahi	[95] [99] [104] [109] [114]
59	Benjamin N. Lee	[80] [85] [91] [94] [100] [101]
60	Chung-Len Lee	[35]
61	Leonard Lee	[61]
62	Hui Li	[85]
63	Jing-Jia Liou	[63]
64	Jiang Brandon Liu	[55] [70] [88]
65	T. M. Mak	[76]
66	Mahesh Mamidipaka	[62] [65] [77]
67	Hratch Mangassarian	[102]
68	Andrew K. Martin	[37] [39] [41] [47] [57]
69	M. Ray Mercer	[61]
70	Hillel Miller	[93]
71	Prabhat Mishra	[68] [79] [90]
72	Cynthia F. Murphy	[13] [18]
73	Vijay Nagasamy	[42]
74	Farid N. Najm	[102]
75	Wayne M. Needham	[22]
76	Joe Newman	[9]
77	Vinit Ogale	[110]
78	Manish Pandey	[17] [24] [58]
79	Ashish Parikh	[12] [13]
80	Ashish R. Parikh	[15]
81	Ganapathy Parthasarathy	[53]
82	Dhiraj K. Pradhan	[42] [81]
83	Carol Pyron	[64]
84	Richard Raimi	[24]
85	Rajesh Raina	[33] [40]
86	Sandip Ray	[97]
87	Hassan K. Reghbati	[1] [2] [3] [4]
88	Elizabeth M. Rudnick	[45]
89	Sean Safarpour	[71] [75] [82] [86] [88] [102]
90	Peter Sandborn	[12] [13] [15] [18]
91	Freescale Semiconductor	[71]
92	Alper Sen	[110] [117]
93	Sep Seyedi	[78]
94	Alexander Smith	[71] [75]
95	Steve Spencer	[9]
96	Nik Sumikawa	[120] [121] [122]
97	Savithri Sundareswaran	[101]
98	Thomas Thomas	[11]
99	Ivor Ting	[48]
100	Spyros Tragoudas	[70]
101	Ekaterina Trofimova	[84] [106]
102	G. Vandling	[72] [73]
103	Mauricio Varea	[81]
104	Prab Varma	[42]
105	Andreas G. Veneris	[48] [49] [52] [55] [71] [74] [75] [78] [82] [86] [88] [102]
106	Praveen Vishakantaiah	[10] [11]
107	Ron G. Walther	[22]
108	Li-C. Wang	[23] [25] [26] [27] [28] [29] [30] [31] [32] [36] [43] [44] [51] [53] [58] [61] [63] [67] [72] [73] [76] [80] [85] [89] [91] [93] [94] [96] [97] [98] [100] [101] [103] [105] [107] [108] [111] [112] [113] [115] [118] [119] [120] [121] [122] [123]
109	Dennis Wassung	[87]
110	Charles H.-P. Wen	[93]
111	Thomas W. Williams	[61]
112	LeRoy Winemberg	[120] [121] [122]
113	Ming Shae Wu	[35]
114	Sean Hsi Yuan Wu	[100]
115	Wen Ching Wu	[35]
116	Jing Zeng	[26] [27] [29] [46] [56] [64] [72] [73]
117	Juhong Zhu	[43] [51] [59] [64]
118	Yervant Zorian	[87]

Colors in the list of coauthors

Last update Fri May 25 03:49:23 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page