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Cristinel Ababei Coauthor index pubzone.org

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DBLP keys2012
27Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLRajendra S. Katti, Cristinel Ababei: Secure Comparison Without Explicit XOR CoRR abs/1204.2854: (2012)
2011
26Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHamed Sajjadi Kia, Cristinel Ababei: A new fault-tolerant and congestion-aware adaptive routing algorithm for regular Networks-on-Chip. IEEE Congress on Evolutionary Computation 2011: 2465-2472
25Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Hamed Sajjadi Kia, Om Prakash Yadav, Jingcao Hu: Energy and reliability oriented mapping for regular Networks-on-Chip. NOCS 2011: 121-128
24Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLHamed Sajjadi Kia, Cristinel Ababei: Improving Fault Tolerance of Network-on-Chip Links via Minimal Redundancy and Reconfiguration. ReConFig 2011: 363-368
2010
23Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei: Network on chip design and optimization using specialized influence models. DAC 2010: 625-626
22Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei: Efficient Congestion-Oriented Custom Network-on-Chip Topology Synthesis. ReConFig 2010: 352-357
21Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVitor de Paulo, Cristinel Ababei: 3D Network-on-Chip Architectures Using Homogeneous Meshes and Heterogeneous Floorplans. Int. J. Reconfig. Comp. 2010: (2010)
2009
20Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei: Parallel placement for FPGAs revisited. FPGA 2009: 280
19Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Rajendra S. Katti: Achieving network on chip fault tolerance by adaptive remapping. IPDPS 2009: 1-4
18Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLVitor de Paulo, Cristinel Ababei: A Framework for 2.5D NoC Exploration Using Homogeneous Networks over Heterogeneous Floorplans. ReConFig 2009: 267-272
17Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei: Speeding Up FPGA Placement via Partitioning and Multithreading. Int. J. Reconfig. Comp. 2009: (2009)
2006
16Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLGang Wang, Satish Sivaswamy, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Elaheh Bozorgzadeh: Statistical Analysis and Design of HARP FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2088-2102 (2006)
15Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Hushrav Mogal, Kia Bazargan: Three-dimensional place and route for FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 25(6): 1132-1140 (2006)
14Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Kia Bazargan: Non-contiguous linear placement for reconfigurable fabrics. IJES 2(1/2): 86-94 (2006)
2005
13Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Hushrav Mogal, Kia Bazargan: Three-dimensional place and route for FPGAs. ASP-DAC 2005: 773-778
12Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLSatish Sivaswamy, Gang Wang, Cristinel Ababei, Kia Bazargan, Ryan Kastner, Eli Bozorgzadeh: HARP: hard-wired routing pattern FPGAs. FPGA 2005: 21-29
11Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Hushrav Mogal, Kia Bazargan: 3D FPGAs: placement, routing, and architecture evaluation (abstract only). FPGA 2005: 263
10Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Yan Feng, Brent Goplen, Hushrav Mogal, Tianpei Zhang, Kia Bazargan, Sachin S. Sapatnekar: Placement and Routing in 3D Integrated Circuits. IEEE Design & Test of Computers 22(6): 520-531 (2005)
9Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPongstorn Maidee, Cristinel Ababei, Kia Bazargan: Timing-driven partitioning-based placement for island style FPGAs. IEEE Trans. on CAD of Integrated Circuits and Systems 24(3): 395-406 (2005)
2004
8Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei: TPR: Three-D Place and Route for FPGAs. FPL 2004: 1172
7Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Pongstorn Maidee, Kia Bazargan: Exploring Potential Benefits of 3D FPGA Integration. FPL 2004: 874-880
6Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Kia Bazargan: Non-Contiguous Linear Placement for Reconfigurable Fabrics. IPDPS 2004
2003
5Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLPongstorn Maidee, Cristinel Ababei, Kia Bazargan: Fast timing-driven partitioning-based placement for island style FPGAs. DAC 2003: 598-603
4Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Kia Bazargan: Placement Method Targeting Predictability Robustness and Performance. ICCAD 2003: 81-85
3Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Kia Bazargan: Timing Minimization by Statistical Timing hMetis-based Partitioning. VLSI Design 2003: 58-63
2002
2Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Kia Bazargan: Statistical Timing Driven Partitioning for VLSI Circuits. DATE 2002: 1109
1Electronic Edition pubzone.org CiteSeerX Google scholar BibTeX bibliographical record in XMLCristinel Ababei, Navaratnasothie Selvakkumaran, Kia Bazargan, George Karypis: Multi-objective circuit partitioning for cutsize and path-based delay minimization. ICCAD 2002: 181-185

Coauthor Index

1Kia Bazargan [1] [2] [3] [4] [5] [6] [7] [9] [10] [11] [12] [13] [14] [15] [16]
2Elaheh Bozorgzadeh (Eli Bozorgzadeh) [12] [16]
3Yan Feng [10]
4Brent Goplen [10]
5Jingcao Hu [25]
6George Karypis [1]
7Ryan Kastner [12] [16]
8Rajendra S. Katti (Raj S. Katti) [19] [27]
9Hamed Sajjadi Kia [24] [25] [26]
10Pongstorn Maidee [5] [7] [9]
11Hushrav Mogal [10] [11] [13] [15]
12Vitor de Paulo [18] [21]
13Sachin S. Sapatnekar [10]
14Navaratnasothie Selvakkumaran [1]
15Satish Sivaswamy [12] [16]
16Gang Wang [12] [16]
17Om Prakash Yadav [25]
18Tianpei Zhang [10]

Colors in the list of coauthors

Last update Fri May 25 03:49:23 2012 CET by the DBLP TeamThis material is Open Data Data released under the ODC-BY 1.0 license — See also our legal information page