Einar J. Aas

	2011
26		Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas: An Enhanced Path Delay Fault Simulator for Combinational Circuits. DSD 2011: 375-381
25		Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas, Mohammad Areef: A programmable BIST with macro and micro codes for embedded SRAMs. EWDTS 2011: 144-150
24		Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas: Design of embedded TCAM based longest prefix match search engine. Microprocessors and Microsystems - Embedded Hardware Design 35(8): 659-667 (2011)
	2010
23		Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas: Path-Delay Fault Testing in Embedded Content Addressable Memories. DSD 2010: 519-524
22		Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas: Experiments with ABIST test methodology applied to path delay fault testing. EWDTS 2010: 59-63
	2009
21		Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas: Design of novel CAM core cell structures for an efficient implementation of low power BCAM system. ACM Great Lakes Symposium on VLSI 2009: 57-62
	2008
20		Sverre Wichlund, Frank Berntsen, Einar J. Aas: Scan Test Response Compaction Combined with Diagnosis Capabilities. J. Electronic Testing 24(1-3): 235-246 (2008)
19		Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verdoolaege, Martin Palkovic, Arnout Vandecappelle, Qubo Hu, Einar J. Aas: Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications. Signal Processing Systems 53(3): 301-321 (2008)
	2007
18		Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Einar J. Aas: Probabilistic gate-level power estimation using a novel waveform set method. ACM Great Lakes Symposium on VLSI 2007: 37-42
	2006
17		Sverre Wichlund, Frank Berntsen, Einar J. Aas: Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor. DFT 2006: 119-127
	2005
16		Oystein Gjermundnes, Einar J. Aas: Remote Path Delay Fault Simulation. DSD 2005: 428-434
	2004
15		Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas: Storage requirement estimation for optimized design of data intensive applications. ACM Trans. Design Autom. Electr. Syst. 9(2): 133-158 (2004)
	2003
14		Øyvind Strøm, Kjetil Svarstad, Einar J. Aas: On the Utilization of Java Technology in Embedded Systems. Design Autom. for Emb. Sys. 8(1): 87-106 (2003)
13		Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas: Data dependency size estimation for use in memory optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 22(7): 908-921 (2003)
	2001
12		Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas: Detection of Partially Simultaneously Alive Signals in Storage Requirement Estimation for Data Intensive Applications. DAC 2001: 365-370
11		Øyvind Strøm, Einar J. Aas: An Implementation of an Embedded Microprocessor Core with Support for Executing Byte Compiled Java Code. DSD 2001: 396-399
	2000
10		Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas: Storage requirement estimation for data intensive applications with partially fixed execution ordering. CODES 2000: 56-60
9		Per Gunnar Kjeldsberg, Francky Catthoor, Einar J. Aas: Automated Data Dependency Size Estimation with a Partially Fixed Execution Ordering. ICCAD 2000: 44-50
8		Einar J. Aas: Design Quality and Design Efficiency; Definitions, Metrics and Relevant Design Experiences. ISQED 2000: 389-394
	1999
7		Øyvind Strøm, Audun Klauseie, Einar J. Aas: A Study of Dynamic Instruction Frequencies in Byte Compiled Java Programs. EUROMICRO 1999: 1232-1235
	1994
6		Einar J. Aas, Tore Steen, Karl Klingsheim: Quantifying Design Quality Through Design Experiments. IEEE Design & Test of Computers 11(1): 27-38 (1994)
	1993
5		Ayman M. Wahba, Einar J. Aas: Verification and Diagnosis of Digital Systems by Termary Reasoning. CHARME 1993: 55-67
	1991
4		Bjørg Reppen, Einar J. Aas: Combined probabilistic testability calculation and compact test generation for PLAs. J. Electronic Testing 2(3): 215-227 (1991)
	1990
3		Ove Brynestad, Einar J. Aas, Anne E. Vallestad: State transition graph analysis as a key to BIST fault coverage. ITC 1990: 537-543
	1978
2		Hedayat Markus Bayegan, Einar J. Aas: An integrated system for interactive editing of schematics, logic simulation and PCB layout design. DAC 1978: 1-8
	1975
1		P. A. Arneberg, Einar J. Aas: Design automation in norway. DAC 1975: 251-256

Coauthor Index

1	Mohammad Areef	[25]
2	P. A. Arneberg	[1]
3	Hedayat Markus Bayegan	[2]
4	Frank Berntsen	[17] [20]
5	Ove Brynestad	[3]
6	Francky Catthoor	[9] [10] [12] [13] [15] [19]
7	Oystein Gjermundnes	[16]
8	Qubo Hu	[19]
9	Per Gunnar Kjeldsberg	[9] [10] [12] [13] [15] [18] [19]
10	Audun Klauseie	[7]
11	Karl Klingsheim	[6]
12	Bjørn B. Larsen	[21] [22] [23] [24] [25] [26]
13	Palanichamy Manikandan	[21] [22] [23] [24] [25] [26]
14	Saeeid Tahmasbi Oskuii	[18]
15	Martin Palkovic	[19]
16	Bjørg Reppen	[4]
17	Tore Steen	[6]
18	Øyvind Strøm	[7] [11] [14]
19	Kjetil Svarstad	[14]
20	Anne E. Vallestad	[3]
21	Arnout Vandecappelle	[19]
22	Sven Verdoolaege	[19]
23	Ayman M. Wahba	[5]
24	Sverre Wichlund	[17] [20]

Colors in the list of coauthors

Last update Fri May 25 03:49:23 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page