VTS 2001: Marina Del Rey, CA, USA

BIST Techniques

Diagnosis Methods

Test Data Compression

Sythesis & Design for Testability

Scan Chain Design

Innovative Measurement Techniques

Diagnosis & Verification ATPG

Defect Analysis and IDDx Diagnosis

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Hot Topic Session

SOC Testing

Online Testing

Self-Test Techniques

Memory Testing

Scalable Fault Simulation, Model Build and ATPG Methods

Test Stimulus Generation for Analog Testing

Hot Topic Session

Embedded Tutorial

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Memory Diagnosis

Minimizing Test Power

Estimating and Reducing Infant Mortality

Novel ATPG Techniques

Test Scheduling, Leakage Estimation and Onchip Delay Measurement

Fault Modeling and BIST Evaluation

Showcase

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