VTS 1997: Monterey, California, USA

VTS 1997: Monterey, California, USA

Core & Processor Test

• K. De:
  Test methodology for embedded cores which protects intellectual property. 2-9
  
• Nur A. Touba, Bahram Pouya:
  Testing Embedded Cores Using Partial Isolation Rings. 10-16
  
• Kazumi Hatayama, Kazunori Hikone, T. Miyazaki, H. Yamada:
  A practical approach to instruction-based test generation for functional modules of VLSI processors. 17-23
  

RAM Test

• V. Kim, T. Chen:
  Assessing SRAM test coverage for sub-micron CMOS technologies. 24-30
  
• H. Goto, S. Nakamura, K. Iwasaki:
  Experimental fault analysis of 1 Mb SRAM chips. 31-36
  
• A. J. van de Goor, Issam B. S. Tlili:
  Disturb Neighborhood Pattern Sensitive Fault. 37-47
  

BIST I

• Albrecht P. Stroele, Frank Mayer:
  Methods to reduce test application time for accumulator-based self-test. 48-53
  
• Franco Fummi, Donatella Sciuto:
  Implicit test pattern generation constrained to cellular automata embedding. 54-59
  
• Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda:
  Cellular automata for deterministic sequential test pattern generation. 60-67
  

Current Testing Techniques

• Rosa Rodríguez-Montañés, Joan Figueras:
  Bridges in sequential CMOS circuits: current-voltage signatur. 68-73
  
• Yiming Gong, Sreejit Chakravarty:
  Using fault sampling to compute I/sub DDQ/ diagnostic test set. 74-79
  
• Claude Thibeault:
  A novel probabilistic approach for IC diagnosis based on differential quiescent current signatures. 80-87
  

Delay Test & Diagnosis

• Liang-Chi Chen, Sandeep K. Gupta, Melvin A. Breuer:
  High Quality Robust Tests for Path Delay Faults. 88-93
  
• Patrick Girard, Christian Landrault, V. Moreda, Serge Pravossoudovitch:
  An optimized BIST test pattern generator for delay testing. 94-100
  
• Xiao-Tao Chen, Fred J. Meyer, Fabrizio Lombardi:
  On the Fault Coverage of Interconnect Diagnosis. 101-109
  

Fault Modeling & Parametric Test

• Yi-Shing Chang, Sandeep K. Gupta, Melvin A. Breuer:
  Analysis of Ground Bounce in Deep Sub-Micron Circuits. 110-116
  
• Peter Dahlgren:
  Switch-level modeling of feedback faults using global oscillation control. 117-122
  
• T. Haulin:
  Built-in parametric test for controlled impedance I/Os. 123-129
  

Verification & Debugging

• Peter Wohl, John A. Waicukauski:
  Using ATPG for clock rules checking in complex scan design. 130-136
  
• Rathish Jayabharathi, Kyung Tek Lee, Jacob A. Abraham:
  A Novel Solution for Chip-Level Functional Timing Verification. 137-142
  
• Shi-Yu Huang, Kuang-Chien Chen, Kwang-Ting Cheng:
  Incremental logic rectification. 143-149
  
• Martin Keim, Michael Martin, Bernd Becker, Rolf Drechsler, Paul Molitor:
  Polynomial Formal Verification of Multipliers. 150-157
  

Analog Test 1

• Abdessatar Abderrahman, Eduard Cerny, Bozena Kaminska:
  CLP-based Multifrequency Test Generation for Analog Circuits. 158-165
  
• Karim Arabi, Bozena Kaminska:
  Parametric and Catastrophic Fault Coverage of Analog Circuits in Oscillation-Test Methodology. 166-171
  
• Zbigniew Jaworski, Mariusz Niewczas, Wieslaw Kuzmicz:
  Extension of Inductive Fault Analysis to Parametric Faults in Analog Circuits with Application to Test Generation. 172-176
  
• Nihal J. Godambe, C.-J. Richard Shi:
  Behavioral level noise modeling and jitter simulation of phase-locked loops with faults using VHDL-AMS. 177-183
  

Panel Session

• J. Borel, M. Cecchini, C. Malipeddi, Janusz Rajski, Yervant Zorian:
  Systems On Silicon: Design and Test Challenges. 184-185
  
• Melvin A. Breuer, Bozena Kaminska, J. McDermid, V. Rayapathi, Donald L. Wheater:
  Will 0.1um Digital Circuits Require Mixed-Signal Testing. 186-187
  

Sequential Circuits Test 1

• Michael S. Hsiao, Elizabeth M. Rudnick, Janak H. Patel:
  Fast Algorithms for Static Compaction of Sequential Circuit Test Vectors. 188-195
  
• Ismed Hartanto, Vamsi Boppana, Janak H. Patel, W. Kent Fuchs:
  Diagnostic Test Pattern Generation for Sequential Circuits. 196-202
  
• Ajay Khoche, Erik Brunvand:
  Critical hazard free test generation for asynchronous circuits. 203-209
  

Concurrent Checking

• Cecilia Metra, Michele Favalli, Bruno Riccò:
  Highly testable and compact single output comparator. 210-215
  
• Xrysovalantis Kavousianos, Dimitris Nikolos:
  Self-exercising self testing k-order comparators. 216-221
  
• Valery A. Vardanian:
  Exact probabilistic analysis of error detection for parity checkers. 222-229
  

Test of Regular Structures

• Michel Renovell, Joan Figueras, Yervant Zorian:
  Test of RAM-based FPGA: methodology and application to the interconnect. 230-237
  
• Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis:
  Robust Sequential Fault Testing of Iterative Logic Arrays. 238-244
  
• C. A. Fleischer, Lee A. Belfore II:
  A new approach for testing artificial neural networks. 245-251
  

Analog Test II

• Christian Dufaza, Hassan Ihs:
  Test Synthesis for DC Test and Maximal Diagnosis of Switched-Capacitor Circuits. 252-260
  
• Pramodchandran N. Variyam, Abhijit Chatterjee, Naveena Nagi:
  Low-cost and efficient digital-compatible BIST for analog circuits using pulse response sampling. 261-266
  
• Soon-Jyh Chang, Chung-Len Lee, Jwu E. Chen:
  Functional test pattern generation for CMOS operational amplifier. 267-273
  

Fault Simulation and Redundancy Identification

• Dilip Krishnaswamy, Elizabeth M. Rudnick, Janak H. Patel, Prithviraj Banerjee:
  SPITFIRE: scalable parallel algorithms for test set partitioned fault simulation. 274-281
  
• Laura Farinetti, Pier Luca Montessoro:
  The Dynamic Rollback Problem in Concurrent Event-Driven Fault Simulation. 282-287
  
• Jian-Kun Zhao, Elizabeth M. Rudnick, Janak H. Patel:
  Static logic implication with application to redundancy identification. 288-295
  

Mixed Signal Test

• Wim Verhaegen, Geert Van der Plas, Georges G. E. Gielen:
  Automated test pattern generation for analog integrated circuits. 296-301
  
• Eduardo J. Peralías, Adoración Rueda, José L. Huertas:
  A DFT Technique for Analog-to-Digital Converters with digital correction. 302-307
  
• W. D. Bartlett:
  Determination of coherence errors in ADC spectral domain testing. 308
  

Panel Session

• Phil Nigh, Wayne M. Needham, Kenneth M. Butler, Peter C. Maxwell, Robert C. Aitken:
  An experimental study comparing the relative effectiveness of functional, scan, IDDq and delay-fault testing. 459
  
• D. Cheung, Bernd Koenemann, S. Nishtala, B. West, D. Wu:
  ATE for VLSI: What Challenges Lie Ahead? 318-319
  
• J. Abraham, P. Frankl, Christian Landrault, Meryem Marzouki, Paolo Prinetto, Chantal Robach, Pascale Thévenod-Fosse:
  Hardware Test: Can We Learn from Software Testing? 320-321
  

Sequential Circuits Test II

• Priyank Kalla, Maciej J. Ciesielski:
  Testability of Sequential Circuits with Multi-Cycle False Path. 322-328
  
• Irith Pomeranz, Sudhakar M. Reddy:
  EXTEST: a method to extend test sequences of synchronous sequential circuits to increase the fault coverage. 329-335
  
• Irith Pomeranz, Sudhakar M. Reddy:
  On n-detection test sequences for synchronous sequential circuits343. 336-343
  

On-Line Testing and Fault-Tolerant Design

• J. Yeandel, D. Thulborn, S. Jones:
  An on-line testable UART implemented using IFIS. 344-349
  
• Andrzej Hlawiczka, Michael Gössel, Egor S. Sogomonyan:
  A linear code-preserving signature analyzer COPMISR. 350-355
  
• Giacomo Buonanno, M. Pugassi, Mariagiovanna Sami:
  A high-level synthesis approach to design of fault-tolerant systems. 356-363
  

Scan and Boundary Scan

• Samy Makar, Edward J. McCluskey:
  ATPG for scan chain latches and flip-flops. 364-369
  
• Robert B. Norwood, Edward J. McCluskey:
  High-Level Synthesis for Orthogonal Sca. 370-375
  
• Chen-Huan Chiang, Sandeep K. Gupta:
  BIST TPGs for Faults in Board Level Interconnect via Boundary Scan. 376-383
  

Testability Analysis

• A. Jee, F. Joel Ferguson:
  A methodolgy for characterizing cell testability. 384-390
  
• V. Prepin, R. David:
  Fault coverage of a long random test sequence estimated from a short simulation. 391-398
  
• Jacob Savir:
  Random pattern testability of memory control logic. 399-409
  

BIST II

• Nur A. Touba:
  Obtaining High Fault Coverage with Circular BIST Via State Skipping. 410-415
  
• Jacob Savir:
  Salvaging test windows in BIST diagnostic. 416-425
  
• Can Ökmen, Martin Keim, Rolf Krieger, Bernd Becker:
  On Optimizing BIST-Architecture by Using OBDD-based Approaches and Genetic Algorithms. 426-433
  

Thermal & Elevated Voltage Testing

• Josep Altet, Antonio Rubio:
  Differential Sensing Strategy for Dynamic Thermal Testing of ICs. 434-439
  
• Vladimir Székely, Márta Rencz, Bernard Courtois:
  Integrating on-chip temperature sensors into DfT schemes and BIST architectures. 440-445
  
• Jonathan T.-Y. Chang, Edward J. McCluskey:
  SHOrt voltage elevation (SHOVE) test for weak CMOS ICs. 446-
  

Panel Session

• Vishwani D. Agrawal, Robert C. Aitken, J. Braden, Joan Figueras, S. Kumar, Hans-Joachim Wunderlich, Yervant Zorian:
  Power Dissipation During Testing: Should We Worry About it? 456-457
  
• Magdy S. Abadir, Jacob A. Abraham, H. Hao, C. Hunter, Wayne M. Needham, Ron G. Walther:
  Microprocessor Test and Validation: Any New Avenues? 458-464
  

Last update Fri May 25 08:47:13 2012 CET by the DBLP Team — Data released under the ODC-BY 1.0 license — See also our legal information page