24. VLSI Design 2011: Chennai, India

• Anant S. Kamath, Vikas Sinha, Sujoy Chakravarty:
  4×2Gbps Source-Synchronous Transmitter in 45nm CMOS. 1-5
  
• Srinivasaraman Chandrasekaran, Kunal Desai, Arul Sendhil, William Ng:
  Self-Calibrating Equalizer for Optimal Jitter Performance Using On-chip Eye Monitoring. 6-11
  
• Mrigank Sharad, P. Vijaya Sankara Rao, Pradip Mandal:
  A New Double Data Rate(DDR) Dual-Mode Duobinary Transmitter Architecture. 12-17
  
• Jeyavijayan Rajendran, Harika Manem, Ramesh Karri, Garrett S. Rose:
  An Approach to Tolerate Process Related Variations in Memristor-Based Applications. 18-23
  
• Kashfia Haque, Paul Beckett:
  A SOI EEPROM Based Configuration Cell with Simple Scrubbing Detection. 24-29
  
• Satyam Dwivedi, Bharadwaj Amrutur, Navakanta Bhat:
  Power Scalable Digital Baseband Architecture for IEEE 802.15.4. 30-35
  
• Diptendu Ghosh, Ranjit Gharpurey:
  Evolution of Oscillation in a Quadrature Oscillator. 36-40
  
• Kunal Desai, Vijay Krishna:
  Quadrature Error Compensation for Jitter Reduction in High Speed Clock and Data Recovery Circuits. 41-46
  
• Biman Chattopadhyay, Anant S. Kamath, Gopalkrishna Nayak:
  A 1.8GHz Digital PLL in 65nm CMOS. 47-51
  
• Subhankar Mukherjee, Pallab Dasgupta:
  Auxiliary State Machines and Auxiliary Functions: Constructs for Extending AMS Assertions. 52-57
  
• Jayanand Asok Kumar, Shobha Vasudevan:
  Variation-Conscious Formal Timing Verification in RTL. 58-63
  
• Maheshwar Chandrasekar, Michael S. Hsiao:
  A Novel Learning Framework for State Space Exploration Based on Search State Extensibility Relation. 64-69
  
• Sachin Shrivastava, Harindranath Parameswaran:
  Improved Timing Windows Overlap Check Using Statistical Timing Analysis. 70-75
  
• Ayan Mandal, Nikhil Jayakumar, Kalyana C. Bollapalli, Sunil P. Khatri, Rabi N. Mahapatra:
  An Automated Approach for Minimum Jitter Buffered H-Tree Construction. 76-81
  
• Ayan Mandal, Vinay Karkala, Sunil P. Khatri, Rabi N. Mahapatra:
  Interconnected Tile Standing Wave Resonant Oscillator Based Clock Distribution Circuits. 82-87
  
• Bhaskar Gopalan:
  A SPICE Macromodel for the Analysis of Lossy Dispersive Coupled GaAs Interconnect Line System. 88-93
  
• Sipra Mandal, Soumya Pandit:
  Statistical Simulation and Modeling of Nano-scale CMOS VCO Using Artificial Neural Network. 94-99
  
• Praveen K. Meduri, Shirshak K. Dhali:
  A Methodology for Automatic Transistor-Level Sizing of CMOS OpAmps. 100-105
  
• M. Zhang, R. Haussler, Markus Olbrich, Harald Kinzelbach, Erich Barke:
  A Statistical Learning Based Modeling Approach and Its Application in Leakage Library Characterization. 106-111
  
• Rahul Rithe, Sharon Chou, Jie Gu, Alice Wang, Satyendra Datla, Gordon Gammie, Dennis Buss, Anantha Chandrakasan:
  Cell Library Characterization at Low Voltage Using Non-linear Operating Point Analysis of Local Variations. 112-117
  
• Palkesh Jain, Ankit Jain:
  Accurate Estimation of Signal Currents for Reliability Analysis Considering Advanced Waveform-Shape Effects. 118-123
  
• Sambit Datta, Ashudeb Dutta, Kunal Datta, Tarun Kanti Bhattacharyya:
  Pseudo Concurrent Quad-Band LNA Operating in 900 MHz/1.8 GHz and 900 MHz/2.4 GHz Bands for Multi-standard Wireless Receiver. 124-129
  
• Shiv Kumar, Vinay Bhaskar Chandratre, Sudheer K. Mohammed, C. K. Pithawa:
  Extraction of Aspect Ratio for Non-Manhattan CMOS Devices. 130-134
  
• Dinesh Ganta, Vignesh Vivekraja, Kanu Priya, Leyla Nazhandali:
  A Highly Stable Leakage-Based Silicon Physical Unclonable Functions. 135-140
  
• Su Myat Min, Jorgen Peddersen, Sri Parameswaran:
  Realizing Cycle Accurate Processor Memory Simulation via Interface Abstraction. 141-146
  
• Swapnil Lotlikar, Vinayak Pai, Paul V. Gratz:
  AcENoCs: A Configurable HW/SW Platform for FPGA Accelerated NoC Emulation. 147-152
  
• Omer Malik, Ahmed Hemani, Muhammad Ali Shami:
  A Library Development Framework for a Coarse Grain Reconfigurable Architecture. 153-158
  
• Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala:
  A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization. 159-164
  
• Yi-Ling Hsieh, Tsung-Yi Ho:
  Automated Physical Design of Microchip-Based Capillary Electrophoresis Systems. 165-170
  
• Sudip Roy, Bhargab B. Bhattacharya, Partha Pratim Chakrabarti, Krishnendu Chakrabarty:
  Layout-Aware Solution Preparation for Biochemical Analysis on a Digital Microfluidic Biochip. 171-176
  
• Kartik Shrivastava, Prabhat Mishra:
  Dual Code Compression for Embedded Systems. 177-182
  
• Kiran Kumar Abburi:
  A Scalable LDPC Decoder on GPU. 183-188
  
• Hussam Amrouch, Joerg Henkel:
  Self-Immunity Technique to Improve Register File Integrity Against Soft Errors. 189-194
  
• Srabanti Pandit, Chandan Kumar Sarkar:
  Modeling the Effect of Gate Fringing and Dopant Redistribution on the Inverse Narrow Width Effect of Narrow Channel Shallow Trench Isolated MOSFETs. 195-200
  
• Subha Chakraborty, T. K. Bhattacharyya:
  Development of a Micro-mechanical Logic Inverter for Low Frequency MEMS Sensor Interfacing. 201-207
  
• K. C. Narasimhamurthy, Roy P. Paily:
  Performance Comparison of Thin-Film Transistors Fabricated Using Different Purity Semiconducting Nanotubes. 208-213
  
• Vignesh Vivekraja, Leyla Nazhandali:
  Feedback Based Supply Voltage Control for Temperature Variation Tolerant PUFs. 214-219
  
• Sreekanth Soman, Amit Brahme, Ramakrishnan Venkatraman, Raashid Shaikh, Santhosh Thiyagaraja, Mahendrasing Patil:
  Ensuring On-Die Power Supply Robustness in High-Performance Designs. 220-225
  
• Pei Liu, Ahmed Hemani, Kolin Paul:
  A Reconfigurable Processor for Phylogenetic Inference. 226-231
  
• Muhammad Adeel Tajammul, Muhammad Ali Shami, Ahmed Hemani, Sridharan Moorthi:
  NoC Based Distributed Partitionable Memory System for a Coarse Grain Reconfigurable Architecture. 232-237
  
• Reeshav Kumar, Yoon Seok Yang, Gwan Choi:
  Intra-Flit Skew Reduction for Asynchronous Bypass Channel in NoCs. 238-243
  
• Michael Trakimas, Sungkil Hwang, Sameer R. Sonkusale:
  Low Power Asynchronous Data Acquisition Front End for Wireless Body Sensor Area Network. 244-249
  
• J. Manikandan, B. Venkataramani, K. Girish, H. Karthic, V. Siddharth:
  Hardware Implementation of Real-Time Speech Recognition System Using TMS320C6713 DSP. 250-255
  
• Tapas Kumar Kundu, Kolin Paul:
  Improving Android Performance and Energy Efficiency. 256-261
  
• V. R. Devanathan, Ishaan Santhosh Shah:
  Hazard-Aware Directed Transition Fault ATPG for Effective Critical Path Test. 262-267
  
• Maheshwar Chandrasekar, Michael S. Hsiao:
  Fault Collapsing Using a Novel Extensibility Relation. 268-273
  
• Aritra Banerjee, Vishwanath Natarajan, Shreyas Sen, Abhijit Chatterjee, Ganesh Srinivasan, Soumendu Bhattacharya:
  Optimized Multitone Test Stimulus Driven Diagnosis of RF Transceivers Using Model Parameter Estimation. 274-279
  
• Zhaobo Zhang, Xrysovalantis Kavousianos, Krishnendu Chakrabarty, Yiorgos Tsiatouhas:
  A Robust and Reconfigurable Multi-mode Power Gating Architecture. 280-285
  
• Michael B. Henry, Robert Lyerly, Leyla Nazhandali, Adam Fruehling, Dimitrios Peroulis:
  MEMS-Based Power Gating for Highly Scalable Periodic and Event-Driven Processing. 286-291
  
• Kyungseok Kim, Vishwani D. Agrawal:
  True Minimum Energy Design Using Dual Below-Threshold Supply Voltages. 292-297
  
• Aarul Jain, Aviral Shrivastava, Chaitali Chakrabarti:
  LA-LRU: A Latency-Aware Replacement Policy for Variation Tolerant Caches. 298-303
  
• S. Banerjee, Jimson Mathew, Dhiraj K. Pradhan, Saraju P. Mohanty, Maciej J. Ciesielski:
  Variation-Aware TED-Based Approach for Nano-CMOS RTL Leakage Optimization. 304-309
  
• Keerthi Kunaparaju, Seetharam Narasimhan, Swarup Bhunia:
  VaROT: Methodology for Variation-Tolerant DSP Hardware Design Using Post-Silicon Truncation of Operand Width. 310-315
  
• Ashis Maity, Amit Patra, Norihisa Yamamura, Jonathan Knight:
  Design of a 20 MHz DC-DC Buck Converter with 84 Percent Efficiency for Portable Applications. 316-321
  
• Anupam Dutta, T. K. Bhattacharyya:
  Low Offset, Low Noise, Variable Gain Interfacing Circuit with a Novel Scheme for Sensor Sensitivity and Offset Compensation for MEMS Based, Wheatstone Bridge Type, Resistive Smart Sensor. 322-327
  
• Vikram Chaturvedi, Bharadwaj Amrutur:
  A Low-Noise Low-Power Noise-Adaptive Neural Amplifier in 0.13um CMOS Technology. 328-333
  
• Weixun Wang, Sanjay Ranka, Prabhat Mishra:
  A General Algorithm for Energy-Aware Dynamic Reconfiguration in Multitasking Systems. 334-339
  
• Vivek D. Tovinakere, Olivier Sentieys, Steven Derrien:
  Wakeup Time and Wakeup Energy Estimation in Power-Gated Logic Clusters. 340-345
  
• Parag Kulkarni, Puneet Gupta, Milos D. Ercegovac:
  Trading Accuracy for Power with an Underdesigned Multiplier Architecture. 346-351
  
• Kanad Basu, Prabhat Mishra:
  Efficient Trace Signal Selection for Post Silicon Validation and Debug. 352-357
  
• Sandesh Prabhakar, Rajamani Sethuram, Michael S. Hsiao:
  Trace Buffer-Based Silicon Debug with Lossless Compression. 358-363
  
• Subhadip Kundu, Santanu Chattopadhyay, Indranil Sengupta, Rohit Kapur:
  Multiple Fault Diagnosis Based on Multiple Fault Simulation Using Particle Swarm Optimization. 364-369
  
• Arvind Jain, Sundarrajan Subramanian, Rubin A. Parekhji, Srivaths Ravi:
  Multi-CoDec Configurations for Low Power and High Quality Scan Test. 370-375
  
• Chunhua Yao, Kewal K. Saluja, Parameswaran Ramanathan:
  Thermal-Aware Test Scheduling Using On-chip Temperature Sensors. 376-381
  
• Kautalya Mishra, Ahmed Faraz, Adit D. Singh:
  Path Delay Tuning for Performance Gain in the Face of Random Manufacturing Variations. 382-388
  

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