21. VLSI Design 2008:
Hyderabad,
India
21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India.
IEEE Computer Society 2008 
Tutorials
- Nidhir Kumar, Senthil N. Velu, Rajan Verma:
Gateway to Chips: High Speed I/O Signalling and Interface.
3-4
- Srikanth Venkataraman, Nagesh Tamarapalli:
DFM / DFT / SiliconDebug / Diagnosis.
5-6
- Shanthi Pavan, Nagendra Krishnapura:
Oversampling Analog-to-Digital Converter Design.
7
- Samarjit Chakraborty, Sethu Ramesh:
Programming and Performance Modelling of Automotive ECU Networks.
8-9
- Vinod Kathail, Tom Miller:
Architecture Exploration for Low Power Design.
10-11
- Adit D. Singh:
Scan Delay Testing of Nanometer SoCs.
13
- Fadi J. Kurdahi, Nikil Dutt, Ahmed M. Eltawil, Sani R. Nassif:
Cross-Layer Approaches to Designing Reliable Systems Using Unreliable Chips.
14-15
- Dwayne Lee:
OpenSPARC - A Scalable Chip Multi-Threading Design.
16
- Vamsi Boppana, Rahoul Varma, S. Balajee:
Implementing the Best Processor Cores.
17-18
Fault Tolerance
- Mojtaba Amiri-Kamalabad, Seyed Ghassem Miremadi, Mahdi Fazeli:
A Power Efficient Approach to Fault-Tolerant Register File Design.
21-26
- Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee:
Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS.
27-32
- Jimson Mathew, Costas Argyrides, Abusaleh M. Jabir, Hafizur Rahaman, Dhiraj K. Pradhan:
Single Error Correcting Finite Field Multipliers Over GF(2m).
33-38
- Aditya Jagirdar, Roystein Oliveira, Tapan J. Chakraborty:
A Robust Architecture for Flip-Flops Tolerant to Soft-Errors and Transients from Combinational Circuits.
39-44
- Kaushal R. Gandhi, Nihar R. Mahapatra:
Energy-Efficient Soft-Error Protection Using Operand Encoding and Operation Bypass.
45-51
Wireless/Communication
Embedded Systems
- Valery Sklyarov, Iouliia Skliarova, Bruno Figueiredo Pimentel, Manuel Almeida:
Multimedia Tools and Architectures for Hardware/Software Co-Simulation of Reconfigurable Systems.
85-90
- Junji Kitamichi, Koji Ueda, Kenichi Kuroda:
A Modeling of a Dynamically Reconfigurable Processor Using SystemC.
91-96
- Jalaj Jain:
A Scalable and Reconfigurable Coprocessor for Image Composition.
97-102
- Alexandru Andrei, Petru Eles, Zebo Peng, Jakob Rosen:
Predictable Implementation of Real-Time Applications on Multiprocessor Systems-on-Chip.
103-110
- Soumyajit Dey, Monu Kedia, Anupam Basu:
An Approach to Software Performance Evaluation on Customized Embedded Processors.
111-117
Technology
- Yogesh Singh Chauhan, Dimitrios Tsamados, Nicolas Abelé, C. Eggimann, Michel J. Declercq, Adrian M. Ionescu:
Compact Modeling of Suspended Gate FET.
119-124
- Aditya Bansal, Jae-Joon Kim, Keunwoo Kim, Saibal Mukhopadhyay, Ching-Te Chuang, Kaushik Roy:
Optimal Dual-VT Design in Sub-100 Nanometer PDSOI and Double-Gate Technologies.
125-130
- Amith Singhee, Jiajing Wang, Benton H. Calhoun, Rob A. Rutenbar:
Recursive Statistical Blockade: An Enhanced Technique for Rare Event Simulation with Application to SRAM Circuit Design.
131-136
- Kewal K. Saluja, Shriram Vijayakumar, Warin Sootkaneung, Xaingning Yang:
NBTI Degradation: A Problem or a Scare?
137-142
- Amlan Ghosh, Rahul M. Rao, Jae-Joon Kim, Ching-Te Chuang, Richard B. Brown:
On-Chip Process Variation Detection Using Slew-Rate Monitoring Circuit.
143-149
Testing/DFT
- Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu:
On Common-Mode Skewed-Load and Broadside Tests.
151-156
- Mohammad Gh. Mohammad, Kewal K. Saluja:
Testing Flash Memories for Tunnel Oxide Defects.
157-162
- Hafizur Rahaman, Dipak K. Kole, Debesh Kumar Das, Bhargab B. Bhattacharya:
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set.
163-168
- Aman Kokrady, C. P. Ravikumar, Nitin Chandrachoodan:
Memory Yield Improvement through Multiple Test Sequences and Application-Aware Fault Models.
169-174
- Irith Pomeranz, Sudhakar M. Reddy:
Design-for-Testability for Improved Path Delay Fault Coverage of Critical Paths.
175-180
- Irith Pomeranz, Sudhakar M. Reddy:
Design-for-Testability for Synchronous Sequential Circuits that Maintains Functional Switching Activity.
181-186
- Nilabha Dev, Sandeep Bhatia, Subhasish Mukherjee, Sue Genova, Vinayak Kadam:
A Partitioning Based Physical Scan Chain Allocation Algorithm that Minimizes Voltage Domain Crossings.
187-193
Interconnects
- Charbel J. Akl, Magdy A. Bayoumi:
Wiring-Area Efficient Simultaneous Bidirectional Point-to-Point Link for Inter-Block On-Chip Signaling.
195-200
- Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest:
Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.
201-207
- Saurav Bandyopadhyay, Pradip Mandal, Stephen E. Ralph, Kenneth Pedrotti:
Integrated TIA-Equalizer for High Speed Optical Link.
208-213
- Jeff Mueller, Resve Saleh:
Single Edge Clock (SEC) Distribution for Improved Latency, Skew, and Jitter Performance.
214-219
- Anish Muttreja, Prateek Mishra, Niraj K. Jha:
Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects.
220-227
- Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen:
Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation.
228-234
- T. Venkata Kalyan, Madhu Mutyam, P. Vijaya Sankara Rao:
Exploiting Variable Cycle Transmission for Energy-Efficient On-Chip Interconnect Design.
235-241
Architecture
- Rupak Samanta, Jason Surprise, Rabi N. Mahapatra:
Dynamic Aggregation of Virtual Addresses in TLB Using TCAM Cells.
243-248
- Hwisung Jung, Massoud Pedram:
Continuous Frequency Adjustment Technique Based on Dynamic Workload Prediction.
249-254
- Iouliia Skliarova, Valery Sklyarov:
Recursive versus Iterative Algorithms for Solving Combinatorial Search Problems in Hardware.
255-260
- Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
Exhaustive Enumeration of Legal Custom Instructions for Extensible Processors.
261-266
- Terrell Bennett, Rama Sangireddy:
An Optimal Multi-Functional Unit Dynamic Instruction Selection Logic at Submicron Technologies.
267-272
- Rajaraman Ramanarayanan, Sanu Mathew, Vasantha Erraguntla, Ram Krishnamurthy, Shay Gueron:
A 2.1GHz 6.5mW 64-bit Unified PopCount/BitScan Datapath Unit for 65nm High-Performance Microprocessor Execution Cores.
273-278
- Hui Wang, Sandeep Baldawa, Rama Sangireddy:
Dynamic Error Detection for Dependable Cache Coherency in Multicore Architectures.
279-285
Analog
- Shubhankar Basu, Balaji Kommineni, Ranga Vemuri:
Mismatch Aware Analog Performance Macromodeling Using Spline Center and Range Regression on Adaptive Samples.
287-293
- Jaime Ramírez-Angulo, Lalitha Mohana Kalyani-Garimella, Annajirao Garimella, Sri Raga Sudha Garimella, Antonio J. López-Martín, Ramón González Carvajal:
An Input Stage for the Implementation of Low-Voltage Rail to Rail Offset Compensated CMOS Comparators.
294-299
- Sri Raga Sudha Garimell:
Highly Linear Wide Dynamic Swing CMOS Transconductance Multiplier Using Source-Degeneration V-I Converters.
300-304
- Rupam Mukherjee, Amit Patra, Soumitro Banerjee:
Chaos-Modulated Ramp IC for EMI Reduction in PWM Buck Converters- Design and Analysis of Critical Issues.
305-310
- Amal Kumar Kundu, Subho Chatterjee, Tarun Kanti Bhattacharyya:
A Fast Settling 100dB OPAMP in 180nm CMOS Process with Compensation Based Optimisation.
311-316
- S. Ramasamy, B. Venkataramani, K. Anbugeetha:
VLSI Implementation of a Digitally Tunable Gm-C Filter with Double CMOS Pair.
317-322
- Sounak Roy, Swapna Banerjee:
A 9 bit 400 MHz CMOS Double-Sampled Sample-and-Hold Amplifier.
323-329
Physical Design/CAD
- Jyotirmoy Ghosh, Siddhartha Mukhopadhyay, Amit Patra, Barry Culpepper, Tawen Mei:
A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts.
331-336
- Pradeep Fernando, Srinivas Katkoori:
An Elitist Non-Dominated Sorting Based Genetic Algorithm for Simultaneous Area and Wirelength Minimization in VLSI Floorplanning.
337-342
- Shashank Prasad:
Fast Congestion Aware Routing for Pin Assignment.
343-347
- Nagaraju Pothineni, Anshul Kumar, Kolin Paul:
A Novel Approach to Compute Spatial Reuse in the Design of Custom Instructions.
348-353
- Banit Agrawal, Timothy Sherwood, Chulho Shin, Simon Yoon:
Addressing the Challenges of Synchronization/Communication and Debugging Support in Hardware/Software Cosimulation.
354-361
Low Power - I
- Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil Dutt:
Incorporating PVT Variations in System-Level Power Exploration of On-Chip Communication Architectures.
363-370
- Sundeepkumar Agarwal, Pavankumar V. K., Yokesh R.:
Energy-Efficient, High Performance Circuits for Arithmetic Units.
371-376
- Qingli Zhang, Jinxiang Wang, Yizheng Ye:
Delay and Energy Efficient Design of On-Chip Encoded Bus with Repeaters.
377-382
- Ankur Gupta, Rajat Chauhan, Vinod Menezes, Vikas Narang, H. M. Roopashree:
A Robust Level-Shifter Design for Adaptive Voltage Scaling.
383-388
- Asral Bahari, Tughrul Arslan, Ahmet T. Erdogan:
Low Power Hardware Architecture for VBSME Using Pixel Truncation.
389-395
NoC/SoC
- Arun Janarthanan, Karen A. Tomko:
MoCSYS: A Multi-Clock Hybrid Two-Layer Router Architecture and Integrated Topology Synthesis Framework for System-Level Design of FPGA Based On-Chip Networks.
397-402
- Hao Shen, Frédéric Pétrot:
MPSoC Communication Architecture Exploration Using an Abstraction Refinement Method.
403-408
- Mahshid Sedghi, Elnaz Koopahi, Armin Alaghi, Mahmood Fathy, Zainalabedin Navabi:
An NoC Test Strategy Based on Flooding with Power, Test Time and Coverage Considerations.
409-414
- Somayyeh Koohi, Mohammad Mirza-Aghatabar, Shaahin Hessabi, Massoud Pedram:
High-Level Modeling Approach for Analyzing the Effects of Traffic Models on Power and Throughput in Mesh-Based NoCs.
415-420
- Deepa Kannan, Aseem Gupta, Aviral Shrivastava, Nikil D. Dutt, Fadi J. Kurdahi:
PTSMT: A Tool for Cross-Level Power, Performance, and Thermal Exploration of SMT Processors.
421-427
Nano
- Fan Wang, Vishwani D. Agrawal:
Single Event Upset: An Embedded Tutorial.
429-434
- Muzaffer O. Simsir, Srihari Cadambi, Franjo Ivancic, Martin Rötteler, Niraj K. Jha:
Fault-Tolerant Computing Using a Hybrid Nano-CMOS Architecture.
435-440
- Rajat Subhra Chakraborty, Somnath Paul, Swarup Bhunia:
Analysis and Robust Design of Diode-Resistor Based Nanoscale Crossbar PLA Circuits.
441-446
- Biswajit Ray, Santanu Mahapatra:
A New Threshold Voltage Model for Omega Gate Cylindrical Nanowire Transistor.
447-452
- Jimson Mathew, Hafizur Rahaman, Babita R. Jose, Dhiraj K. Pradhan:
Design of Reversible Finite Field Arithmetic Circuits with Error Detection.
453-459
Verification
- Yinlei Yu, Cameron Brien, Sharad Malik:
Exploiting Circuit Reconvergence through Static Learning in CNF SAT Solvers.
461-468
- Chi-Un Lei, Ngai Wong:
Efficient Linear Macromodeling via Discrete-Time Time-Domain Vector Fitting.
469-474
- Abhishek Datta, Vigyan Singhal:
Formal Verification of a Public-Domain DDR2 Controller Design.
475-480
- Pejman Lotfi-Kamran, Mehran Massoumi, Mohammad Mirzaei, Zainalabedin Navabi:
Enhanced TED: A New Data Structure for RTL Verification.
481-486
- Kyuho Shim, Kesava R. Talupuru, Maciej J. Ciesielski, Seiyang Yang:
Simulation Acceleration with HW Re-Compilation Avoidance.
487-491
- Roopak Sinha, Partha S. Roop, Samik Basu:
A Module Checking Based Converter Synthesis Approach for SoCs.
492-501
Low Power - II
- Mohammed Shareef I, Pradeep Nair, Bharadwaj Amrutur:
Energy Reduction in SRAM using Dynamic Voltage and Frequency Management.
503-508
- S. A. Kannan, N. S. Sreeram, Bharadwaj S. Amrutur:
Unified Vdd - Vth Optimization Based DVFM Controller for a Logic Block.
509-514
- Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Temperature and Process Variations Aware Power Gating of Functional Units.
515-520
- Sriram Sambamurthy, Jacob A. Abraham, Raghuram S. Tupuri:
A Robust Top-Down Dynamic Power Estimation Methodology for Delay Constrained Register Transfer Level Sequential Circuits.
521-526
- Yuanlin Lu, Vishwani D. Agrawal:
Total Power Minimization in Glitch-Free CMOS Circuits Considering Process Variation.
527-532
- Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula:
Power Reduction of Functional Units Considering Temperature and Process Variations.
533-539
Architecture/Arithmetic
- Pejman Lotfi-Kamran, Amir-Mohammad Rahmani, Ali-Asghar Salehpour, Ali Afzali-Kusha, Zainalabedin Navabi:
Stall Power Reduction in Pipelined Architecture Processors.
541-546
- Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas:
A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.
547-552
- T. S. Rajesh Kumar, C. P. Ravikumar, R. Govindarajan:
Memory Architecture Exploration Framework for Cache Based Embedded SOC.
553-559
- Satish Anand Verkila, Siva Kumar Bondada, Bharadwaj S. Amrutur:
A 100MHz to 1GHz, 0.35V to 1.5V Supply 256 x 64 SRAM Block Using Symmetrized 9T SRAM Cell with Controlled Read.
560-565
- Ashis Kumer Biswas, Md. Mahmudul Hasan, Moshaddek Hasan, Ahsan Raja Chowdhury, Hafiz Md. Hasan Babu:
A Novel Approach to Design BCD Adder and Carry Skip BCD Adder.
566-571
- Sabyasachi Das, Sunil P. Khatri:
A Merged Synthesis Technique for Fast Arithmetic Blocks Involving Sum-of-Products and Shifters.
572-579
Design/MEMS/Optical
Synthesis
- Anish Muttreja, Srivaths Ravi, Niraj K. Jha:
Variability-Tolerant Register-Transfer Level Synthesis.
621-628
- Jimson Mathew, Hafizur Rahaman, Ashutosh Kumar Singh, Abusaleh M. Jabir, Dhiraj K. Pradhan:
A Galois Field Based Logic Synthesis Approach with Testability.
629-634
- Sabyasachi Das, Sunil P. Khatri:
A Timing-Driven Synthesis Technique for Arithmetic Product-of-Sum Expressions.
635-640
- Vyas Krishnan, Srinivas Katkoori:
Clock Period Minimization with Iterative Binding Based on Stochastic Wirelength Estimation during High-Level Synthesis.
641-646
- Almitra Pradhan, Ranga Vemuri:
On the Use of Hash Tables for Efficient Analog Circuit Synthesis.
647-652
- Sabyasachi Das, Sunil P. Khatri:
An Inversion-Based Synthesis Approach for Area and Power Efficient Arithmetic Sum-of-Products.
653-659
Low Power - III
- Kaushik Bhattacharyya, Pradip Mandal:
A Low Voltage, Low Ripple, on Chip, Dual Switch-Capacitor Based Hybrid DC-DC Converter.
661-666
- Janakiraman Viraraghavan, Bishnu Prasad Das, Bharadwaj Amrutur:
Voltage and Temperature Scalable Standard Cell Leakage Models Based on Stacks for Statistical Leakage Characterization.
667-672
- Charbel J. Akl, Magdy A. Bayoumi:
Self-Sleep Buffer for Distributed MTCMOS Design.
673-678
- Yan Gu, Samarjit Chakraborty:
Power Management of Interactive 3D Games Using Frame Structures.
679-684
- Bishnu Prasad Das, Janakiraman Viraraghavan, Bharadwaj Amrutur, H. S. Jamadagni, N. V. Arvind:
Voltage and Temperature Scalable Gate Delay and Slew Models Including Intra-Gate Variations.
685-691
Security
Invited Special Session:
Standards in EDA
- Nagi Naganathan:
Standards in EDA: An Introduction.
727
- Shrenik Mehta:
Industry Standards from Accellera.
728
- Dennis Brophy:
IEEE Market-Oriented Standards Process and the EDA Industry.
729
- John Goodenough:
Design Automation Standards: The IP Providers Perspective.
730
- Sri Chandra:
Driving Analog Mixed Signal Verification through Verilog-AMS.
731
- Kathy Werner:
VSI Standards, Current Status and Future Work.
732
Last update Wed Feb 15 04:24:59 2012
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