14. VLSI Design 2001: Bangalore, India

Tutorials

• Noel Menezes, Sachin S. Sapatnekar: Optimization and Analysis Techniques for the Deep Submicron Regime. 3-4
• Doris Keitel-Schulz, Norbert Wehn, Francky Catthoor, Preeti Ranjan Panda: Embedded Memories in System Design: Technology, Application, Design and Tools. 5-6
• Sudipta Bhawmik: ntroduction to SystemC. 7-8
• Anand Raghunathan, Sujit Dey: Low-Power Mobile Wireless Communication System Design: Protocols, Architectures, and Design Methodologies. 9-10
• Ruchira Kamdar, Seetharam Gundurao, Rajiv V. Joshi, N. S. Murty: IBM's Blue Logic Design Methodology-Circuits and Physical Design. 11-12
• Deepak Kataria: Next Generation Network Processors. 13-15
• Mahesh Mehendale, Santhosh Kumar Amanna: Functional Verification of Programmable DSP Cores. 16-17
• V. Ranganatha, R. Sunda: System Level Testability Issues of Core Based System-on-a-Chip. 18
• Ramesh Harjani, Jackson Harvey: Tutorial: CMOS Analog Circuits for Wireless Communications. 18

Embedded Systems I

• Anupam Rastogi, M. Balakrishnan, Anshul Kumar:
  Integrating Communication Cost Estimation in Embedded Systems Design : A PCI Case Study. 23-28
  
• Kanishka Lahiri, Sujit Dey, Anand Raghunathan:
  Evaluation of the Traffic-Performance Characteristics of System-on-Chip Communication Architectures. 29-35
  
• Ajit Gupte, Mahesh Mehendale, Ramesh Ramamritham, Deepa Nair:
  Performance Considerations in Embedded DSP based System-On-a-Chip Designs. 36-41
  
• Abhijit K. Deb, Ahmed Hemani, Johnny Öberg, Adam Postula, Dan Lindqvist:
  Hardware Software Codesign of DSP System Using Grammar Based Approach. 42-47
  
• Koen Danckaert, Chidamber Kulkarni, Francky Catthoor, Hugo De Man, Vivek Tiwari:
  A Systematic Approach for System Bus Load Reduction Applied to Medical Imaging. 48-
  

Embedded Systems II

• Debashis Panigrahi, Sujit Dey, Ramesh R. Rao, Kanishka Lahiri, Carla-Fabiana Chiasserini, Anand Raghunathan:
  Battery Life Estimation of Mobile Embedded Systems. 57-63
  
• Pavan Kumar, Mani B. Srivastava:
  Power-aware Multimedia Systems using Run-time Prediction. 64-69
  
• Prabhat Mishra, Peter Grun, Nikil D. Dutt, Alexandru Nicolau:
  Processor-Memory Co-Exploration driven by a Memory-Aware Architecture Description Language. 70-75
  
• Manoj Kumar Jain, M. Balakrishnan, Anshul Kumar:
  ASIP Design Methodologies : Survey and Issues. 76-
  

SOC Methodologies

• G. Surendra, S. K. Nandy, Paul Sathya:
  ReDeEm_RTL: A Software Tool for Customizing Soft Cells for Embedded Applications. 85-90
  
• Vineet Sahula, C. P. Ravikumar:
  The Hierarchical Concurrent Flow Graph Approach for Modeling and Analysis of Design Processes. 91-96
  
• Anupam Datta, Sidharth Choudhury, Anupam Basu, Hiroyuki Tomiyama, Nikil Dutt:
  Satisfying Timing Constraints of Preemptive Real-Time Tasks through Task Layout Technique. 97-102
  
• Anand L. D'Souza, Michael S. Hsiao:
  Error Diagnosis of Sequential Circuits Using Region-Based Mode. 103-
  

Test I

• Ruifeng Guo, Irith Pomeranz, Sudhakar M. Reddy:
  On Improving Static Test Compaction for Sequential Circuits. 111-116
  
• Sitaram Yadavalli, Sandip Kundu:
  On Fault-Simulation Through Embedded Memories On Large Industrial Designs. 117-121
  
• Debabrata Bagchi, Dipanwita Roy Chowdhury, Joy Mukherjee, Santanu Chattopadhyay:
  A Novel Strategy to Test Core Based Designs. 122-127
  
• Debesh Kumar Das, Bhargab B. Bhattacharya, Satoshi Ohtake, Hideo Fujiwara:
  Testable Design of Sequential Circuits with Improved Fault Efficiency. 128-133
  
• Sameer Sharma, Michael S. Hsiao:
  Combination of Structural and State Analysis for Partial Scan. 134-
  

Test II

• Yong Chang Kim, Kewal K. Saluja, Vishwani D. Agrawal:
  Combinational Test Generation for Acyclic SequentialCircuits using a Balanced ATPG Model. 143-148
  
• Srivaths Ravi, Niraj K. Jha:
  Synthesis of System-on-a-chip for Testability. 149-156
  
• Arun Krishnamachary, Jacob A. Abraham, Raghuram S. Tupuri:
  Timing Verification and Delay Test Generation for Hierarchical Designs. 157-162
  
• Jian-Kun Zhao, Jeffrey A. Newquist, Janak H. Patel:
  A Graph Traversal Based Framework For Sequential Logic Implication With An Application To C-Cycle Redundancy Identification. 163-
  

Verification

• Wolfgang Günther, Rolf Drechsler:
  Implementation of Read- k-times BDDs on Top of Standard BDD Packages. 173-178
  
• Siddharth R. Phanse, R. K. Shyamasundar:
  Application of Esterel for Modelling and Verification of Cachet Protocol on CRF Memory Model. 179-188
  
• Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr:
  Design Verification and Functional Testing of FiniteState Machines. 189-195
  
• Rajiv V. Joshi, Wei Hwang, Andreas Kuehlmann:
  Design Of Provably Correct Storage Arrays. 196-
  

Low-Power I

• Rex Min, Manish Bhardwaj, Seong-Hwan Cho, Eugene Shih, Amit Sinha, Alice Wang, Anantha Chandrakasan:
  Low-Power Wireless Sensor Networks. 205-210
  
• Hendrawan Soeleman, Kaushik Roy, Bipul Chandra Paul:
  Sub-Domino Logic: Ultra-Low Power Dynamic Sub-Threshold Digital Logic. 211-214
  
• Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali:
  Average Power in Digital CMOS Circuits using Least Square Estimation. 215-220
  
• Amit Sinha, Anantha Chandrakasan:
  Dynamic Voltage Scheduling Using Adaptive Filtering of Workload Traces. 221-226
  
• Nikhil Tripathi, Amit M. Bhosle, Debasis Samanta, Ajit Pal:
  Optimal Assignment of High Threshold Voltage for Synthesizing Dual Threshold CMOS Circuits. 227-
  

Low-Power II

• Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar:
  Accurate Power Macro-modeling Techniques for Complex RTL Circuits. 235-241
  
• Abhijit M. Lele, S. K. Nandy:
  Architecture of Reconfigurable a Low Power Gigabit AT Switch. 242-247
  
• David Duarte, Narayanan Vijaykrishnan, Mary Jane Irwin, Mahmut T. Kandemir:
  Formulation and Validation of an Energy Dissipation Model for the Clock Generation Circuitry and Distribution Networks. 248-253
  
• Vishal Dalal, C. P. Ravikumar:
  Software Power Optimizations In An Embedded System. 254-
  

Analog Design

• Sree Ganesan, Ranga Vemuri:
  Library Binding for High-Level Synthesis of Analog Systems. 261-268
  
• Jackson Harvey, Ramesh Harjani:
  An Integrated Quadrature Mixer with Improved Image Rejection at Low Voltage. 269-273
  
• Sanjay Mohan, Michael L. Bushnell:
  A Code Transition Delay Model for ADC Test. 274-282
  
• Alper Demir, David E. Long, Jaijeet S. Roychowdhury:
  Computing Phase Noise Eigenfunctions Directly from Harmonic Balance/Shooting Matrices. 283-
  

FPGA

• K. Yan:
  Logic Synthesis for CPLDs and FPGAs with PLA-Style Logic Blocks. 291-298
  
• Malay Haldar, Anshuman Nayak, Alok N. Choudhary, Prithviraj Banerjee, U. Nagaraj Shenoy:
  Fpga Hardware Synthesis From Matlab. 299-304
  
• U. Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary, Mahmut T. Kandemir:
  Efficient Synthesis of Array Intensive Computations onto FPGA Based Accelerators. 305-310
  
• Wolfgang Günther, Rolf Drechsler:
  Performance Driven Optimization for MUX based FPGAs. 311-316
  
• Sujatha Sundararaman, Sriram Govindarajan, Ranga Vemuri:
  Application Specific Macro Based Synthesis. 317-
  

Physical Design I

• Qinwei Xu, Pinaki Mazumder, Mayukh Bhattacharya:
  Modeling of Nonuniform Interconnects by Using Differential Quadrature Method. 327-332
  
• Sujit T. Zachariah, Sreejit Chakravarty:
  A Novel Algorithm for Multi-Node Bridge Analysis of Large VLSI Circuits. 333-338
  
• Mark A. Hillebrand, Thomas Schurger, Peter-Michael Seidel:
  How to Half Wire Lengths in the Layout of Cyclic Shifter. 339-344
  
• Koushik Sinha, Susmita Sur-Kolay, Bhargab B. Bhattacharya, P. S. Dasgupta:
  Partitioning Routing Area into Zones with Distinct Pins. 345-
  

Physical Design II

• Sabyasachi Sengupta, Somavalli Ramanathan, Biswadeep Chatterjee, Dibyendu Goswami:
  Minimizing Area and Maximizing Porosity for Cell Layouts Using Innovative Routing Strategies. 353-358
  
• Qinwei Xu, Pinaki Mazumder, Zheng-Fan Li:
  Transmission Line Modeling by Modified Method of Characteristics. 359-364
  
• Nagaraj Ns, Poras T. Balsara, Cyrus D. Cantrell:
  Crosstalk Noise Verification in Digital Designs with Interconnect Process Variations. 365-370
  
• Marcello Lajolo, Matteo Sonza Reorda, Massimo Violante:
  Early Evaluation Of Bus Interconnects Dependability For System-On-Chip Designs. 371-
  

Built-In Test

• Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das:
  An Efficient Parallel Transparent Bist Method For Multiple Embedded Memory Buffers. 379-384
  
• Dilip K. Bhavsar, Rishan Tan:
  Observability Register Architecture For Efficient Production Test And Debug Of Vlsi Circuits. 385-390
  
• Thomas Clouqueur, Ozen Ercevik, Kewal K. Saluja, Hiroshi Takahashi:
  Efficient Signature-Based Fault Diagnosis Using Variable Size Windows. 391-396
  
• Der-Cheng Huang, Wen-Ben Jone, Sunil R. Das:
  A Parallel Built-In Self-Diagnostic Method For Embedded Memory Buffers. 397-402
  
• Biplab K. Sikdar, Purnabha Majumder, Monalisa Mukherjee, Parimal Pal Chaudhuri, Debesh K. Das, Niloy Ganguly:
  Hierarchical Cellular Automata As An On-Chip Test Pattern Generator. 403-
  

Synthesis

• Vikas Agrawal, Anand Pande, Mahesh Mehendale:
  High Level Synthesis Of Multi-Precision Data Flow Graphs. 411-416
  
• L. Wang, A. E. A. Almaini:
  Multilevel Logic Minimization Using Functional Don't Cares. 417-424
  
• Supratik Chakraborty, Rajeev Murgai:
  Complexity Of Minimum-Delay Gate Resizing. 425-430
  
• Krishnendu Chakrabarty, Andrew Exnicios, Rajatish Mukherjee:
  Synthesis Of Transparent Circuits For Hierarchical An System-On-A-Chip Test. 431-
  

Architecture

• Masa-Aki Fukase, Ryusuke Egawa, Tomoaki Sato, Tadao Nakamura:
  Scaling Up Of Wave Pipelines. 439-445
  
• Alexander Worm, Holger Lamm, Norbert Wehn:
  Vlsi Architectures For High-Speed Map Decoders. 446-453
  
• Biplab K. Sikdar, Purnabha Majumder, Parimal Pal Chaudhuri, Niloy Ganguly:
  Design Of Multiple Attractor Gf (2p) Cellular AutomataFor Diagnosis Of Vlsi Circuits. 454-459
  
• Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busa:
  Synthesizing A Long Latency Unit Within Vliw Processor. 460-
  

Technology I

• Omkaram Nalamasu, Pat G. Watson, Raymond A. Cirelli, Jeff Bude, Isik C. Kizilyalli, Ross A. Kohler: Invited Paper: Extending Resolution Limits of IC Fabrication Technology: Demonstration by Device Fabrication and Circuit Performance. 469-469
• Mayukh Bhattacharya, Pinaki Mazumder, Ronald J. Lomax:
  Fd-Tlm Electromagnetic Field Simulation Of High-Speed Iii-V Heterojunction Bipolar Transistor Digital Logic Gates. 470-474
  
• G. Shrivastav, S. Mahapatra, V. Ramgopal Rao, J. Vasi, K. G. Anil, C. Fink, Walter Hansch, I. Eisele:
  erformance Optimization Of 60 Nm Channel Length Vertical Mosfets Using Channel Engineering. 475-478
  
• Nihar R. Mohapatra, A. Dutta, Madhav P. Desai, V. Ramgopal Rao:
  Effect Of Fringing Capacitances In Sub 100 Nm Mosfet's With High-K Gate Dielectrics. 479-
  

Technology II

• R. K. Jarwal, Durga Misra:
  Degradation Of Nmosfets During High-Field Injection With Reverse Biased Voltage At Source And Drain Junctions. 485-490
  
• B. Prasad, P. J. George, Chandra Shekhar:
  High Frequency Behaviour Of Electron Transport In Silicon And Its Implication For Drain Conductance Of Mos Transistors. 491-494
  
• Pratheep A. Nair, Anubhav Gupta, Madhav P. Desai:
  An On-Chip Coupling Capacitance Measurement Technique. 495-499
  
• Shabbir H. Batterywala, H. Narayanan:
  Spectral Algorithm To Compute And Synthesize Reduced Order Passive Models For Arbitrary Rc Multiports. 500-
  

Deep Sub-Micron

• Dinesh Pamunuwa, Hannu Tenhunen:
  Repeater Insertion To Minimise Delay In Coupled Interconnects. 513-517
  
• N. V. Arvind, P. R. Suresh, V. Sivakumar, Chandrani Pal, Debaprasad Das:
  Integrated Crosstalk And Oxide Integrity Analysis In Dsm Designs. 518-523
  
• Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni:
  Switching Noise Analysis Framework For High Speed Logic Families. 524-530
  
• V. Sankara Subramanian, C. P. Ravikumar:
  Estimating Crosstalk From Vlsi Layouts. 531-
  

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