Session 1 Arithmetic

• 
  T. Sato, M. Nakajima, T. Sukemura, G. Goto: A Regularly Structured 54-bit Modified-Wallace-Tree Multiplier. 1-10
• 
  Alain Guyot, Y. Kusumaputri: OCAPI: A Prototype for High Precision Arithmetic. 11-18

Session 2 Digital Signal Processing

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  O. C. McNally, John V. McCanny, Roger F. Woods: Design of a Highly Pipelined 2nd Order IIR Filter Chip. 19-28
• 
  Jens Sparsø, Steen Pedersen, Erik Paaske: Design of a Fully Parallel Viterbi Decoder. 29-38
• 
  R. Nagalla, Laurence E. Turner: Pipelined BIT-Serial SYNthesis of Digital Filerting Algorithms. 39-48

Session 3a Formal Methods

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  Jerry R. Burch, Edmund M. Clarke, David E. Long: Symbolic Model Checking with Partitioned Transistion Relations. 49-58
• 
  Eleanor M. Mayger, Michael P. Fourman: Integration of Formal Methods with System Design. 59-69
• 
  Geraint Jones, Mary Sheeran: Deriving Bit-Serial Circuits in Ruby. 71-80
• 
  Klaus Schneider, Ramayya Kumar, Thomas Kropf: Structurein Hardware Proofs: Fist Steps Towards Automation in a Higher-Order Environment. 81-90

Session 3b Physical Design

• 
  Konrad Doll, Frank M. Johannes, Georg Sigl: DOMINO: Deterministic Placement Improvement with Hill-Climbing Capabilities. 91-100
• 
  Stefan Mayrhofer, Massoud Pedram, Ulrich Lauther: A Flow-Oriented Approach to the Placement of Boolean Networks. 101-110
• 
  Habib Youssef, Rung-Bin Lin, Eugene Shragowitz: Bounds on Net Delays for Physical Design of Fast Circuits. 111-118
• 
  Karl-Heinz Erhard, Frank M. Johannes: Area Minimisation of IC Power/Ground Nets by Topology Optimisation. 119-126

Session 4a Simulation

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  Herbert Bauer, Christian Sporrer, Thomas H. Krodel: On Distributed Logic Simulation Using Time Warp. 127-136
• 
  Erik Brunvand, M. Starkey: An Integrated Environment for the Design and Simulation of Self-Timed Systems. 137-146
• 
  Tom J. Kazmierski, Andrew D. Brown, Ken G. Nichols, Mark Zwolinski: A General Purpose Network Solving System. 147-156

Session 4b Vision and Neural Architectures

• 
  Peter B. Denyer, David S. Renshaw, Gouyu Wang, Ming Ying Lu, Stuart Anderson: On-Chip CMOS Sensors for VLSI Imaging Systems. 157-166
• 
  J. Quali, Gabriele Saucier, P. Y. Alla, Jacques Trilhe, L. Masse-Navette: A Customizable Neural Processor for Distributed Neural Network. 167-176
• 
  Daniele D. Caviglia, Maurizio Valle, Giacomo M. Bisio: A VLSI Module for Analog Adaptive Neural Architectures. 177-186

Keynote Paper

• 
  A. Richard Newton: Has CAD for VLSI Reached a Dead End? 187-192

Session 5 High Level Synthesis

• 
  Werner Geurts, Stefaan Note, Francky Catthoor, Hugo De Man: Partitioning-Based Allocation of Dedicated Data-Paths in the Architectural Synthesis for High Throughput Applications. 193-202
• 
  Norbert Wehn, J. Biesenack, Michael Pilsl: A New Approach to Multiplexer Minimisation in the CALLAS Synthesis Environment. 203-213

Session 6a Modelling for Synthesis

• 
  Ahmed Amine Jerraya, Pierre G. Paulin, Simon Curry: Meta VHDL for Higher Level Controller Modeling and Synthesis. 215-224
• 
  Philip A. Wilsey, Timothy J. McBrayer, David Sims: Towards a Formal Model of VLSI Systems Compativle with VHDL. 225-236
• 
  Wolfgang Glunz, Gerd Venzl: Hardware Design Using CASE Tools. 237-246

Session 6b Processor Design

• 
  A. Laudenbach, Manfred Glesner, Norbert Wehn: A VLSI System Design for the Control of High Performance Combustion Engines. 247-256
• 
  Patrice Frison, Dominique Lavenier: A Fully Integrated Systolic Spelling Co-Processor. 257-266
• 
  Wolfram Liebsch, K. Boettcher: Parallel Architecture and VLSI Implementation of a 80MHz 2D-DCT 80 MHz 2D-DCT/ICDT Processor. 267-275

Session 7 RT-Level Synthesis

• 
  Bill Lin, A. Richard Newton: Exact Redundant State Registers Removal Based on Binary Decision Diagrams. 277-286
• 
  P. F. Yeung, D. J. Rees: Resources Restricted Global Scheduling. 287-296
• 
  Mirjam Schönfeld, Markus Schwiegershausen, Peter Pirsch: Synthesis of Intermediate Memories needed for the Data Supply to Processor Arrays. 297-306
• 
  Marina Zanella, Paolo Gubian: Workspace and Methodology Management in the Octtools Environment. 307-316

Session 8a Routing

• 
  Jan Madsen: Single-Level Wiring for CMOS Functional Cells. 317-326
• 
  Ravi R. Pai, S. S. S. P. Rao: An Over-the-Cell Channel Router. 327-336
• 
  M. Starkey, Tony M. Carter: Switchbox Routing by Pattern Matching. 337-346

Session 8b VLSI Arrays

• 
  Donald F. Beal, Costas Lambrinoudakis: GPFP: A SIMD PE for Higher VLSI Densities. 347-356
• 
  Wayne P. Burleson, Louis L. Scharf: Input/Output Design for VLSI Array Architectures. 357-366
• 
  Anders Færgemand Nielsen, Poul Martin Rands Jensen, Kallol Kumar Bagchi, Ole Olsen: Comparing Transformation Schemes for VLSI Array Processor Design - A Case Study. 367-376

Keynote Paper

• 
  Mitsumasa Koyanagi: A New Chip Architecture for VLSIs - Optical Coupled 3D Common Memory and Optical Interconnections. 377-386

Session 9 Circuit Design 1

• 
  Farhad Aghdasi: Pass-Transistor Self-Clocked Asynchronous Sequential Circuits. 387-395
• 
  C. Thomas Gray, Thomas A. Hughes, Sanjay Arora, Wentai Liu, Ralph K. Cavin III: Theoretical and Practical Issues in CMOS Wave Pipelining. 397-409

Session 10 Circuit Design 2

• 
  Naser Awad, David R. Smith: Automatic Interfacing of Synchronous Modules to an Asynchronous Environment. 411-420
• 
  Bernhard Klaassen: How to Compare Analog Results. 421-428
• 
  Bulent I. Dervisoglu, Gayvin E. Stong: Application of Scan-Based DFT Methodology for Detecting Static and Timing Failures in VLSI Components. 429-438

Session 11 Logic Synthesis and Timing Optimisation

• 
  Sujit Dey, Franc Brglez, Gershon Kedem: Identification and Resynthesis of Pipelines in Sequential Networks. 439-449
• 
  Albert van der Werf, B. T. McSweeney, Jef L. van Meerbergen, Paul E. R. Lippens, Wim F. J. Verhaegh: Hierarchical Retiming Including Pipelining. 451-460
• 
  Ellen Sentovich, Robert K. Brayton: Preserving Don't Care Conditions During Retiming. 461-470

Session 12 Fault Tolerant Arrays

• 
  Manfred Schimmler, Hartmut Schmeck: A Fault Tolerant and High Speed Instruction Systolic Array. 471-480
• 
  Guoning Liao: A Reconfigurable Fault Tolerant Module Approach to the Reliability Enhancement for Mesh Connected Processor Arrays. 481-490
• 
  Ian P. Jalowiecki, Stephen J. Hedge: The WASP 2 Wafer Scale Integration Demonstrator. 491-500

last updated on Sat May 18 05:40:51 2013 by the dblp team
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