4. SLIP 2002: San Diego, CA, USA

@proceedings{DBLP:conf/slip/2002,
  title     = {The Fourth IEEE/ACM International Workshop on System-Level Interconnect
               Prediction (SLIP 2002), April 6-7, 2002, San Diego, California,
               Proceedings},
  booktitle = {SLIP},
  publisher = {ACM},
  year      = {2002},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Expanding Rentian Analysis

• Stephen E. Krufka, Phillip Christie:
  Terminal optimization analysis for functional block re-use. 3-8
  
• Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout:
  Getting more out of Donath's hierarchical model for interconnect prediction. 9-16
  
• Tianpei Zhang, Sachin S. Sapatnekar:
  Optimized pin assignment for lower routing congestion after floorplanning phase. 17-21
  
• Amit Singh, Malgorzata Marek-Sadowska:
  FPGA interconnect planning. 23-30
  

The X Architecture: Not your father's diagonal wiring

• Steven L. Teig:
  The X architecture: not your father's diagonal wiring. 33-37
  

Estimation Needs for Future Networking Systems Interconnect

• Sudhakar Muddu:
  Estimation needs for future networking systems interconnect. 41-44
  

Power Grid and Signal Integrity Analysis

• Andrey V. Mezhiba, Eby G. Friedman:
  Scaling trends of on-chip Power distribution noise. 47-53
  
• Sani R. Nassif, Onsi Fakhouri:
  Technology trends in power-grid-induced noise. 55-59
  
• Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim:
  Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects. 61-68
  

Reconfigurable Interconnect for Next Generation Systems

• Ingrid Verbauwhede, M.-C. Frank Chang:
  Reconfigurable interconnect for next generation systems. 71-74
  

Using Prediction for Performance Optimization and Estimation

• Murat R. Becer, David Blaauw, Ibrahim N. Hajj, Rajendran Panda:
  Early probabilistic noise estimation for capacitively coupled interconnects. 77-83
  
• Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng:
  Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction. 85-89
  
• Muzammil Iqbal, Ahmed Sharkawy, Usman Hameed, Phillip Christie:
  Stochastic wire length sampling for cycle time estimation. 91-96
  
• Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie:
  Wire layer geometry optimization using stochastic wire sampling. 97-102
  

Interconnect Exploration for Future Wire Dominated Technologies

• Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex:
  Interconnect exploration for future wire dominated technologies. 105-106
  

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