DSP Architectures

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  Camille Leroux, Christophe Jégo, Patrick Adde, Michel Jézéquel, Deepak Gupta: A highly parallel Turbo Product Code decoder without interleaving resource. 1-6
• 
  Junfeng Fan, Ingrid Verbauwhede: A digit-serial architecture for inversion and multiplication in GF(2^M). 7-12
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  Yang Sun, Joseph R. Cavallaro: Unified decoder architecture for LDPC/turbo codes. 13-18
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  Xinmiao Zhang, Jiangli Zhu: Efficient interpolration architecture for soft-decision Reed-Solomon decoding by applying slow-down. 19-24
• 
  Ching-Te Chiu, Tsun-Hsien Wang, Wei-Ming Ke, Chen-Yu Chuang, Jhih-Siao Huang, Wei-Su Wong, Ren-Song Tsay: A 100MHz real-time tone mapping processor with integrated photographic and gradient compression in 0.13 mum technology. 25-30
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  Frederik Naessens, Bruno Bougard, Siebert Bressinck, Lieven Hollevoet, Praveen Raghavan, Liesbet Van der Perre, Francky Catthoor: A unified instruction set programmable architecture for multi-standard advanced forward error correction. 31-36

Poster Session 1

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  Radomir Jakovljevic, Aleksandar Beric: A method for improving the efficiency of a two-level memory hierarchy. 37-42
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  Julien A. Vijverberg, Peter H. N. de With: Hardware acceleration for tracking by computing low-order geometric moments. 43-48
• 
  Lanping Deng, Chi-Li Yu, Chaitali Chakrabarti, Jungsub Kim, Vijaykrishnan Narayanan: Efficient image reconstruction using partial 2D Fourier transform. 49-54
• 
  Mohammad M. Mansour: Parallel channel interleavers for 3GPP2/UMB. 55-60
• 
  Myung Hun Lee, Jae Hee Han, Myung Hoon Sunwoo: New simplified sum-product algorithm for low complexity LDPC decoding. 61-66
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  Mahdi Shabany, P. Glenn Gulak: A systolic architecture of a Sequential Monte Carlo-based equalizer for frequency-selective MIMO channels. 67-72
• 
  Chih-Hao Chao, Chun-Yuan Chu, An-Yeu Wu: Location-Constrained Particle Filter human positioning and tracking system. 73-76
• 
  Weiguo Tang, Lei Wang: Cooperative OFDM for energy-efficient wireless sensor networks. 77-82
• 
  Chun-Yu Chen, Cheng-Hung Lin, An-Yeu Wu: High-throughput dual-mode single/double binary map processor design for wireless wan. 83-87
• 
  Robert Priewasser, Mario Huemer, Bruno Bougard: Trade-off analysis of decoding algorithms and architectures for multi-standard LDPC decoder. 88-93

Coding and Communications

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  Bainan Chen, Xinmiao Zhang, Zhongfeng Wang: Error correction for multi-level NAND flash memory using Reed-Solomon codes. 94-99
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  Nikos Kanistras, Vassilis Paliouras: Impact of roundoff error on the decisions of the Log Sum-Product algorithm for LDPC decoding. 100-105
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  Xuebin Wu, Zhiyuan Yan, Yuan Xie: Two-dimensional crosstalk avoidance codes. 106-111
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  Stanley Yuan-Shih Chen, Nam-Seog Kim, Jan M. Rabaey: Multi-mode sub-Nyquist rate digital-to-analog conversion for direct waveform synthesis. 112-117
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  Min Li, David Novo, Bruno Bougard, Frederik Naessens, Liesbet Van der Perre, Francky Catthoor: An implementation friendly low complexity multiplierless LLR generator for soft MIMO sphere decoders. 118-123
• 
  Lei Ma, Kevin Dickson, John McAllister, John V. McCanny, Mathini Sellathurai: Reduced-complexity MSGR-based matrix inversion. 124-128
• 
  Yi Luo, Mehmet Celenk: Kalman filtering based motion estimation for video coding with adaptive block partitioning. 129-134
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  Shin Wang Ho, Sung Dae Kim, Myung Hoon Sunwoo: Fast multiple reference frame selection methods for H.264/AVC. 135-139
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  Renfei Liu, Keshab K. Parhi: Minimal complexity low-latency architectures for Viterbi decoders. 140-145
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  Yongmei Dai, Zhiyuan Yan: Efficient ordering schemes for sphere decoder. 146-151
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  Chao-Chung Cheng, Chia-Kai Liang, Yen-Chieh Lai, Homer H. Chen, Liang-Gee Chen: Analysis of belief propagation for hardware realization. 152-157
• 
  Chi-Wei Lin, Yu-Han Chen, Liang-Gee Chen: Bio-inspired unified model of visual segmentation system for CAPTCHA character recognition. 158-163

Poster Session 2

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  Dandan Ding, Lu Yu, Christophe Lucarz, Marco Mattavelli: Video decoder reconfigurations and AVS extensions in the new MPEG reconfigurable video coding framework. 164-169
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  Gwo Giun Lee, He-Yuan Lin, Ming-Jiun Wang, Bo-Han Chen, Yuan-Long Cheng: On the verification of multi-standard SoC'S for reconfigurable video coding based on algorithm/architecture co-exploration. 170-175
• 
  Carl von Platen, Johan Eker: Efficient realization of a cal video decoder on a mobile terminal (position paper). 176-181
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  Jani Boutellier, Veeranjaneyulu Sadhanala, Christophe Lucarz, Philip Brisk, Marco Mattavelli: Scheduling of dataflow models within the Reconfigurable Video Coding framework. 182-187
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  Jianjun Li, Dandan Ding, Christophe Lucarz, Samuel Keller, Marco Mattavelli: Efficient data flow variable length decoding implementation for the MPEG reconfigurable video coding framework. 188-193
• 
  Shuo Wang, Jianwei Dai, Lei Wang: Defect-tolerant digital filtering with unreliable molecular electronics. 194-199
• 
  Ting-Jung Lin, Shu-Yen Lin, An-Yeu Wu: Traffic-balanced IP mapping algorithm for 2D-mesh On-Chip-Networks. 200-203
• 
  Seung Seob Yeom, JongSuk Choi, Yoon Seob Lim, Mignon Park: DSP implementation of probabilistic sound source localization. 204-209
• 
  Kai Zhang, Xinming Huang, Chen Shen: Soft decoder architecture of LT codes. 210-215
• 
  Jinjin He, Zhongfeng Wang, Huaping Liu: Low-complexity high-speed 4-D TCM decoder. 216-220
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  Rami A. Abdallah, Naresh R. Shanbhag: Error-resilient low-power Viterbi decoders via state clustering. 221-226
• 
  Jie Chen, Keshab K. Parhi: Further cost reduction of adaptive echo and next cancellers for high-speed Ethernet transceivers. 227-232

Design Methods

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  Stephen McKeown, Roger Woods, John McAllister: Power efficient dynamic-range utilisation for DSP on FPGA. 233-238
• 
  Bin Jiang, Ed F. Deprettere, Bart Kienhuis: Hierarchical run time deadlock detection in process networks. 239-244
• 
  David Novo, Min Li, Bruno Bougard, Frederik Naessens, Liesbet Van der Perre, Francky Catthoor: Application-driven adaptive fixed-point refinement for SDRs. 245-250
• 
  Perttu Salmela, Harri Sorokin, Jarmo Takala: Low-complexity polynomials modulo integer with linearly incremented variable. 251-256
• 
  Cao Liang, Xin-Ming Huang: SmartCell: A power-efficient reconfigurable architecture for data streaming applications. 257-262

Special Session on SOCS and DSPS with Multiple Cores

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  Kun-Yuan Hsieh, Yen-Chih Liu, Chi-Hua Lai, Jenq Kuen Lee: The support of software design patterns for streaming RPC on embedded multicore processors. 263-268
• 
  Bhavana B. Manjunath, Aaron S. Williams, Chaitali Chakrabarti, Antonia Papandreou-Suppappola: Efficient mapping of advanced signal processing algorithms on multi-processor architectures. 269-274
• 
  Yen-Kuang Chen, Wenlong Li, Xiaofeng Tong: Parallelization of AdaBoost algorithm on multi-core processors. 275-280

Special Session on Reconfigurable Video Coding

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  Ghislain Roquier, Matthieu Wipliez, Mickaël Raulet, Jörn W. Janneck, Ian D. Miller, David B. Parlour: Automatic software synthesis of dataflow program: An MPEG-4 simple profile decoder case study. 281-286
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  Jörn W. Janneck, Ian D. Miller, David B. Parlour, Ghislain Roquier, Matthieu Wipliez, Mickaël Raulet: Synthesizing hardware from dataflow programs: An MPEG-4 simple profile decoder case study. 287-292
• 
  Mickaël Raulet, Jonathan Piat, Christophe Lucarz, Marco Mattavelli: Validation of bitstream syntax and synthesis of parsers in the MPEG Reconfigurable Video Coding framework. 293-298

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