SiPS 2006: Banff, Alberta, Canada

• Mohamad Sawan:
  Signal Processing Based Implantable Microsystems for Intracortical Therapeutic Purposes.
  
• Craig S. Lent:
  Molecular quantum-dot cellular automata.
  

Software Define Radio

• V. Torres, A. Perez-Pascual, T. Sansaloni, Javier Valls:
  Design of high performance timing recovery loops for communication applications. 1-4
  
• Andrew K. C. Kwan, Slim Boumaiza, Michael R. Smith, Fadhel M. Ghannouchi:
  Automating the Verification of SDR Base band Signal Processing Algorithms Developed on DSP/FPGA Platform. 5-9
  
• Ivan Corretjer, Chia-Jui Hsu, Shuvra S. Bhattacharyya:
  Configuration and Representation of Large-Scale Dataflow Graphs using the Dataflow Interchange Format. 10-15
  
• Min Li, Bruno Bougard, Francky Catthoor:
  Exploit Multiple-Domain Sparseness for HSDPA Chip Level Equalization in SDR: Algorithm and DSP Implementation. 16-21
  
• Yuan Lin, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Alastair Reid, Krisztián Flautner:
  Design and Implementation of Turbo Decoders for Software Defined Radio. 22-27
  

Multiple-Input-Multiple-Output (MIMO) wireless systems I

• Yuping Zhang, Jun Tang, Keshab K. Parhi:
  Low Complexity List Updating Circuits for List Sphere Decoders. 28-33
  
• Mohamed Elfituri, Walaa Hamouda, Ali Ghrayeb:
  Performance Analysis of a New Transmission Scheme for Multi-Relay Channels. 34-38
  
• Amirhossein Alimohammad, Bruce F. Cockburn:
  A Reconfigurable SOS-based Rayleigh Fading Channel Simulator. 39-44
  
• Jian-Hung Lin, Keshab K. Parhi:
  Low complexity iterative joint detection, decoding, and channel estimation for wireless MIMO system. 45-50
  
• Xiang Nian Zeng, Ali Ghrayeb:
  Maximum Likelihood Estimation of Carrier Frequency Offset in Correlated MIMO OFDM Systems. 51-55
  

ASIC and Architectures

• Zhiyuan Yan, Dilip V. Sarwate:
  Reduced-Complexity Pipelined Architectures for Finite Field Inversions. 56-61
  
• Yu-Hung Lee, Tzu-Hao Yu, Kuo-Ken Huang, An-Yeu Wu:
  Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems. 62-65
  
• Logan M. Rakai, Jianhua Li, Laleh Behjat, Jie Huang:
  A Structural Study and Hyperedge Clustering Technique for Large Scale Circuits. 66-70
  
• Hoseok Chang, Junho Cho, Wonyong Sung:
  Performance Evaluation of an SIMD Architecture with a Multi-bank Vector Memory Unit. 71-76
  
• Zhiyuan Yan:
  Digit-Serial Systolic Architectures for Inversions over GF(2m). 77-82
  
• Yuming Zhu, Yanni Chen, Dale E. Hocevar, Manish Goel:
  A Reduced-Complexity, Scalable Implementation of Low Density Parity Check (LDPC) Decoder. 83-88
  
• Fan-Min Li, Cheng-Hung Lin, An-Yeu Wu:
  A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold. 89-94
  
• Ruchir Gupte, William W. Edmonson, Senanu Ocloo, Winser E. Alexander:
  Pipelined ALU for Signal Processing to Implement Interval Arithmetic. 95-100
  

HDTV

• Kenji Goto, Atsushi Hatabu, Hirofumi Nishizuka, Katsumasa Matsunaga, Ryoichi Nakamura, Yoji Mochizuki, Takashi Miyazaki:
  H.264 Video Encoder Implementation on a Low-power DSP with Low and Stable Computational Complexity. 101-106
  
• Youngsoo Kim, William Edmonson:
  H.264 Video Decoder Design: Beyond RTL Design Implementation. 107-112
  
• Jianpeng Dong, Nam Ling:
  An Iterative Method for Frame-Level Adaptive Wiener Interpolation Filters in Video Coding. 113-117
  
• Fengling Li, Nam Ling, Stephen A. Chiappari:
  A Theoretical Model and Study of Weighted MCTF Residual Energy. 118-123
  
• Kwang Woo Lee, Sung Dae Kim, Myung Hoon Sunwoo:
  VSIP : Video Specific Instruction Set Processor for H.264/AVC. 124-129
  
• Nicolas Beucher, Normand Bélanger, Yvon Savaria, Guy Bois:
  Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. 130-135
  

Programmable and Reconfigurable DSP Architectures

• William N. Chelton, Mohammed Benaissa:
  High-Speed Pipelined EGG Processor on FPGA. 136-141
  
• Timo Vogt, Norbert Wehn:
  A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding. 142-147
  
• Jeenong Yang, Seerap A. Savari, Oskar Mencercv:
  Lossless Compression Using Two-Level and Multilevel Boolean Minimization. 148-152
  
• William N. Chelton, Mohammed Benaissa:
  Limiting Flexibility in Multiplication over GF(2m): A Design Methodology. 153-156
  
• Rafal Dlugosz, Krzysztof Iniewski, Tomasz Talaska:
  0.35 m 22W Multiphase Programmable Clock Generator for Circular Memory SC FIR Filter For Wireless Sensor Applications. 157-160
  

Multiple-Input-Multiple-Output (MIMO) wireless systems II

• Jarlath Ifiok Umoh, Tokunbo Ogunfunmi:
  Semi-Blind Channel Estimation for OFDM using Least Squares. 161-164
  
• Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, Wen-Chiang Chen:
  A Robust Band-Tracking Packet Detector (BT-PD) in OFDM-Based Ultra-Wideband Systems. 165-170
  
• Jyh-Ting Lai, Chun-Yuan Chu, An-Yeu Wu, Wen-Chiang Chen:
  A Low Cost Packet Detector in OFDM-Based Ultra-Wideband Systems. 171-176
  
• Haideh M. Karkhanechi, Bernard C. Levy:
  EM-based Channel Estimation for Space Time Block Coded MIMO OFDM Systems. 177-181
  
• Lin Qiang, Nigel M. Allinson:
  FPGA Implementation of Pipelined Architecture for Optical Imaging Distortion Correction. 182-187
  

Low Power

• Li-Hsun Chen, Oscal T.-C. Chen:
  A Low-Power Folded Programmable FIR Architecture. 188-193
  
• Keith Boyle, Sai Mohan Kilambi, Rafal Dlugosz, Kris Iniewski, Vincent C. Gaudet:
  An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters. 194-199
  
• Konstantina Karagianni, Vassilis Paliouras, Theodoros Giannopoulos:
  Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems. 200-204
  
• Yang Liu, Tong Zhang, Jiang Hu:
  Low Power Trellis Decoder with Overscaled Supply Voltage. 205-208
  

Coding and Compression

• Spyros Gidaros, Vassilis Paliouras:
  Simplified Criteria for Early Iterative Decoding Termination. 209-214
  
• Javad Haghighat, Walaa Hamouda, M. Reza Soleymani:
  Fixed-to-Variable Length Source Coding Using Turbo Codes. 215-219
  
• Ning Chen, Yongmei Dai, Zhiyuan Yan:
  Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes. 220-225
  
• Saeed Sharifi Tehrani, Bruce F. Cockburn, Stephen Bates:
  On the Effects of Colored Noise on the Performance of LDPC Codes. 226-231
  
• Yair Linn:
  An Optimal Adaptive M-PSK Carrier Phase Detector Suitable for Fixed-Point Hardware Implementation within FPGAs and ASICs. 232-237
  

System On Chip

• Samuel Evain, Jean-Philippe Diguet, Milad El Khodary, Dominique Houzet:
  Automated derivation of NoC Communication Specifications from Application Constraints. 238-243
  
• Farhat Thabet, Philippe Coussy, Dominique Heller, Eric Martin:
  Design Space Exploration of DSP Applications Based on Behavioral Description Models. 244-249
  
• Ari Kulmala, Erno Salminen, Marko Hännikäinen, Timo D. Hämäläinen:
  Evaluating SoC Network Performance in MPEG-4 Encoder. 250-255
  
• A. K. Riemens, René J. van der Vleuten, Pieter van der Wolf, G. Jacob, Jan-Willem van de Waerdt, J. G. Janssen:
  Transparent Embedded Compression in Systems-on-Chip. 256-261
  
• Daesun Oh, Keshab K. Parhi:
  Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes. 262-267
  
• Lin Qiang, Nigel M. Allinson:
  Spatial Optical Distortion Correction in an FPGA. 268-273
  

Design Methodologies and CAD Tools for VLSI signal processing systems

• Ramsey Hourani, Ravi Jenkal, W. Rhett Davis, Winser Alexander:
  Automated Architectural Exploration for Signal Processing Algorithms. 274-279
  
• Caaliph Andriamisaina, Bertrand Le Gal, Emmanuel Casseau:
  Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. 280-285
  
• Yin-Tsung Hwang, Jiun-Yan Chen, Ming-Hwa Sheu:
  Automatic Generation of Programmable Parallel CRC & Scrambler Designs. 286-291
  
• Tom Vander Aa, Murali Jayapala, Henk Corporaal, Francky Catthoor, Geert Deconinck:
  Instruction Transfer And Storage Exploration for Low Energy VLIWs. 292-297
  

Industrial Applications

• Ali Yazdanpanah, Rodney G. Vaughan:
  Fault Tolerance of Quantized Unitary Precoders. 298-302
  
• Wei Liu, Junrye Rho, Wonyong Sung:
  Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories. 303-308
  
• Ming-Feng Hsu, Yen-Liang Chen, Kai-Yuan Jheng, An-Yeu Wu:
  A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System. 309-312
  
• Tokunbo Ogunfunmi, Thomas K. Paul:
  On the Convergence of the Frequency-Domain LMS Adaptive Filter using LMS-DFT. 313-320
  

Programmable and Reconfigurable DSP Architectures

• Milan Tichý, Jan Schier, David Gregg:
  FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic. 321-326
  
• Heikki Hurskainen, Jari Nurmi:
  SystemC Model of an Interoperative GPS/Galileo Code Correlator Channel. 327-332
  
• Yong-Kyu Jung:
  Desing and Optimization of a Programmable Instruction Decoder for DSP Architecture. 333-338
  
• Romain Michard, Arnaud Tisserand, Nicolas Veyrat-Charvillon:
  Carry Prediction and Selection for Truncated Multiplication. 339-344
  
• Yen-Chin Liao, Hsie-Chia Chang, Chih-Wei Liu:
  Carry Estimation for Two's Complement Fixed-Width Multipliers. 345-350
  
• Thomas Schuster, D. N. Bruna, Bruno Bougard, V. Derudder, A. Hoffmann, Liesbet Van der Perre:
  Subword-Parallel VLIW Architecture Exploration for Multimode Software Defined Radio. 351-356
  

Image and Machine Vision

• Jun Cai, Muzamil S. Pervez, Mohamed S. Shehata, Robert Johannesson, Wael M. Badawy, Ahmad Radmanesh:
  On The Identification of Snow Movements on Roads. 357-361
  
• Bert Geelen, Aris Ferentinos, Francky Catthoor, Arnout Vandecappelle, Gauthier Lafruit, Thanos Stouraitis, Rudy Lauwereins, Diederik Verkest:
  Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications. 362-367
  
• Choudhury A. Rahman, Wael M. Badawy:
  An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC Encoder. 368-371
  
• Qi Xiaoping, Zhang Qiheng, Ouyang Yimin, Ma Jiaguang:
  A Method for Object Tracking using Shape Matching. 372-376
  
• Choong Jin Hyun, Sung Dae Kim, Myung Hoon Sunwoo:
  Efficient Memory Reuse and Sub-Pixel Interpolation Algorithms for ME/MC of H.264/AVC. 377-382
  
• Sumeer Goel, Yasser Ismail, Parimal Devulapalli, Jason McNeely, Magdy A. Bayoumi:
  An Efficient Data Reuse Motion Estimation Engine. 383-386
  

Programmable and Reconfigurable DSP Architectures

• Geoff Knagge, Mark Bickerstaff, Brett Ninness, Steven R. Weller, Graerne Woodward:
  A VLSI 8×8 MIMO Near-ML Decoder Engine. 387-392
  
• Ada S. Y. Poon:
  An Energy-Efficient Reconfigurable Baseband Processor for Flexible Radios. 393-398
  
• Bruno Bougard, Gregory Lenoir, Antoine Dejonghe, Liesbet Van der Perre, Francky Catthoor, Wim Dehaene:
  SmartMIMO: Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Wireless Local Area Networks. 399-404
  
• Yuming Zhu, Chaitali Chakrabarti:
  Architecture-Aware LDPC Code Design for Software Defined Radio. 405-410
  

ASIC and Architectures

• Jie Chen, Keshab K. Parhi:
  Adaptive Tap Management in Multi-Gigabit Echo & Next Cancellers. 411-415
  
• Tomasz Talaska, Ryszard Wojtyna, Rafal Dlugosz, Krzysztof Iniewski, Witold Pedrycz:
  Analog-Counter-Based Conscience Mechanism in Kohonen's Neural Network Implemented in CMOS 0.18 m Technology. 416-421
  
• Tzu-Hao Yu, Chi-Li Yu, Kai-Yuan Jheng, An-Yeu Wu:
  On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems. 422-427
  
• Yu-Wei Chang, Chih-Chi Cheng, Chun-Chia Chen, Hung-Chi Fang, Liang-Gee Chen:
  Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture. 428-433
  
• Theodoros Giannopoulos, Vassilis Paliouras:
  A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information. 434-439
  

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