SCOPES 2003: Vienna, Austria

Andreas Krall (Ed.): Software and Compilers for Embedded Systems, 7th International Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003, Proceedings. Lecture Notes in Computer Science 2826 Springer 2003, ISBN 3-540-20145-9

@proceedings{DBLP:conf/scopes/2003,
  editor    = {Andreas Krall},
  title     = {Software and Compilers for Embedded Systems, 7th International
               Workshop, SCOPES 2003, Vienna, Austria, September 24-26, 2003,
               Proceedings},
  booktitle = {SCOPES},
  publisher = {Springer},
  series    = {Lecture Notes in Computer Science},
  volume    = {2826},
  year      = {2003},
  isbn      = {3-540-20145-9},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Invited Talk

James C. Dehnert:
The Transmeta Crusoe: VLIW Embedded in CISC. 1

Code Size Reduction

Qin Zhao, Bart Mesman, Henk Corporaal:
Limited Address Range Architecture for Reducing Code Size in Embedded Processors. 2-16
Warren Cheung, William S. Evans, Jeremy Moses:
Predicated Instructions for Code Compaction. 17-32
Sheayun Lee, Jaejin Lee, Sang Lyul Min, Jason Hiser, Jack W. Davidson:
Code Generation for a Dual Instruction Set Processor Based on Selective Code Transformation. 33-48

Code Selection

Erik Eckstein, Oliver König, Bernhard Scholz:
Code Instruction Selection Based on SSA-Graphs. 49-65
Hiroaki Tanaka, Shinsuke Kobayashi, Yoshinori Takeuchi, Keishi Sakanushi, Masaharu Imai:
A Code Selection Method for SIMD Processors with PACK Instructions. 66-80
Björn Decker, Daniel Kästner:
Reconstructing Control Flow from Predicated Assembly Code. 81-100

Loop Optimizations

Stefaan Himpe, Francky Catthoor, Geert Deconinck:
Control Flow Analysis for Recursion Removal. 101-116
Litong Song, Krishna M. Kavi, Ron Cytron:
An Unfolding-Based Loop Optimization Technique. 117-132
Gang-Ryung Uh:
Tailoring Software Pipelining for Effective Exploitation of Zero Overhead Loop Buffer. 133-150

Automatic Retargeting

Yunheung Paek, Minwook Ahn, Soonho Lee:
Case Studies on Automatic Extraction of Target-Specific Architectural Parameters in Complex Code Generation. 151-166
Oliver Wahlen, Manuel Hohenauer, Gunnar Braun, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Xiaoning Nie:
Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. 167-181

System Design

Arshad Jhumka, Neeraj Suri, Martin Hiller:
A Framework for the Design and Validation of Efficient Fail-Safe Fault-Tolerant Programs. 182-197
Hiroo Ishikawa, Tatsuo Nakajima:
A Case Study on a Component-Based System and Its Configuration. 198-210
Kirk Schloegel, David Oglesby, Eric Engstrom, Devesh Bhatt:
Composable Code Generation for Model-Based Development. 211-225
Ioannis Charitakis, Dionisios N. Pnevmatikatos, Evangelos P. Markatos, Kostas G. Anagnostakis:
Code Generation for Packet Header Intrusion Analysis on the IXP1200 Network Processor. 226-239

Register Allocation

Johan Runeson, Sven-Olof Nyström:
Retargetable Graph-Coloring Register Allocation for Irregular Architectures. 240-254
Dae-Hwan Kim, Hyuk-Jae Lee:
Fine-Grain Register Allocation Based on a Global Spill Costs Analysis. 255-269

Offset Assignment

V. V. N. S. Sarvani, R. Govindarajan:
Unified Instruction Reordering and Algebraic Transformations for Minimum Cost Offset Assignment. 270-284
Desiree Ottoni, Guilherme Ottoni, Guido Araujo, Rainer Leupers:
Improving Offset Assignment through Simultaneous Variable Coalescing. 285-297

Analysis and Profiling

Raimund Kirner, Peter P. Puschner:
Transformation of Meta-Information by Abstract Co-interpretation. 298-312
Richard Stahl, Robert Pasko, Luc Rijnders, Diederik Verkest, Serge Vernalde, Rudy Lauwereins, Francky Catthoor:
Performance Analysis for Identification of (Sub-)Task-Level Parallelism in Java. 313-328

Analysis and Profiling

Kevin Casey, David Gregg, M. Anton Ertl, Andrew Nisbet:
Towards Superinstructions for Java Interpreters. 329-343
Ming-Yung Ko, Shuvra S. Bhattacharyya:
Partitioning for DSP Software Synthesis. 344-358

Memory and Cache Optimizations

Viera Sipková:
Efficient Variable Allocation to Dual Memory Banks of DSPs. 359-372
Diego Andrade, Basilio B. Fraguela, Ramon Doallo:
Cache Behavior Modeling of Codes with Data-Dependent Conditionals. 373-387
Marco Garatti:
FICO: A Fast Instruction Cache Optimizer. 388-402

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