Low power design

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  Vojin G. Oklobdzija: Computing at the ultimate low-energy limits. 1
• 
  Deepak Kumar, Pankaj Kumar, Manisha Pattanaik: Performance analysis of dynamic threshold MOS (DTMOS) based 4-input multiplexer switch for low power and high speed FPGA design. 2-7
• 
  Bertrand Le Gal, Aurélien Ribon, Lilian Bossuet, Dominique Dallet: Reducing and smoothing power consumption of ROM-based controller implementations. 8-13

Analog and RF circuits

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  Stanley S. K. Ho, Carlos E. Saavedra: A 5.4 GHz fully-integrated low-noise mixer. 14-17
• 
  Francisco de Assis Brito Filho, Fernando Rangel de Sousa: Wideband ring VCO for cognitive radio five-port receiver. 18-22
• 
  Shaahin Haddadi Nejad, Ziaaddin Daie Kouzeh Kanani, Jafar Sobhi, Iman Salami Fard, Kuresh Ghanbari: A high speed, highly linear CMOS fully differential track and hold circuit. 23-27
• 
  Guillermo Costa, Alfredo Arnaud, Matías R. Miguez: A precision autozero amplifier for EEG signals. 28-32

Analog and mixed-signal design

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  André Luís Fortunato, Carlos Alberto dos Reis Filho: A -60dB THD/100MHz true unity-gain voltage buffer CMOS circuit. 33-36
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  Antonio Colaci, Gianluigi Boarin, Andrea Roggero, Lorenzo Civardi, Carlo Roma, Andreas Ripp, Michael Pronath, Gunter Strube: Systematic analysis & optimization of analog/mixed-signal circuits balancing accuracy and design time. 37-42
• 
  Dalton Martini Colombo, Gilson Inacio Wirth, Christian Jesús B. Fayomi: Design methodology using inversion coefficient for low-voltage low-power CMOS voltage reference. 43-48
• 
  Vinicius Callegaro, Felipe de Souza Marques, Carlos Eduardo Klock, Leomar Soares da Rosa Jr., Renato P. Ribas, André Inácio Reis: SwitchCraft: a framework for transistor network design. 49-53

Testing

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  Magdy S. Abadir: Design for reality: knowledge discovery in design and test data. 54
• 
  Sobeeh Almukhaizim, Mohammad Gh. Mohammad, Mohammad Khajah: Low-power test in compression-based reconfigurable scan architectures. 55-60
• 
  Andrea Calimera, Enrico Macii, Danilo Ravotto, Ernesto Sánchez, Matteo Sonza Reorda: Generating power-hungry test programs for power-aware validation of pipelined processors. 61-66

Multiprocessor SoCs

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  Chenjie Yu, Peter Petrov: Adaptive multi-threading for dynamic workloads in embedded multiprocessors. 67-72
• 
  Gabriel Marchesan Almeida, Sameer Varyani, Rémi Busseuil, Gilles Sassatelli, Pascal Benoit, Lionel Torres, Everton Carara, Fernando Gehm Moraes: Evaluating the impact of task migration in multi-processor systems-on-chip. 73-78
• 
  Bruno Cruz de Oliveira, Márcio Eduardo Kreutz, Edgard de Faria Corrêa, Ivan Saraiva Silva: Exploring memory organization in virtual MP-SoC platforms. 79-84

NoC design and evaluation

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  Leonardo Kunz, Gustavo Girão, Flávio Rech Wagner: Evaluation of a hardware transactional memory model in an NoC-based embedded MPSoC. 85-90
• 
  Leonel Tedesco, Thiago R. da Rosa, Fabien Clermidy, Ney Calazans, Fernando Gehm Moraes: Implementation and evaluation of a congestion aware routing algorithm for networks-on-chip. 91-96
• 
  Johanna Sepúlveda, Marius Strum, Wang Jiang Chau, Ricardo Pires: The LRD traffic impact on the NoC-based SoCs. 97-102

Digital design

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  Dirk Koch, Christian Beckhoff, Jim Torresen: Zero logic overhead integration of partially reconfigurable modules. 103-108
• 
  Denis Teixeira Franco, Maí Correia Vasconcelos, Lirida A. B. Naviner, Jean-François Naviner: On evaluating the signal reliability of self-checking arithmetic circuits. 109-114
• 
  Rafael Soares, Ney Laert Vilar Calazans, Victor Lomné, Amine Dehbaoui, Philippe Maurine, Lionel Torres: A GALS pipeline DES architecture to increase robustness against DPA and DEMA attacks. 115-120
• 
  Daniel Gomes Mesquita, Guilherme Perin, Fernando Luís Herrmann, João Baptista dos Santos Martins: An efficient implementation of montgomery powering ladder in reconfigurable hardware. 121-126

Design reliability issues

• 
  Fadi J. Kurdahi: Designing working systems with imperfect chips. 127
• 
  Maurício Banaszeski da Silva, Gilson I. Wirth: Modeling the impact of RTS on the reliability of ring oscillators. 128-133
• 
  Gabriel de M. Borges, Luiz Fernando Gonçalves, Tiago R. Balen, Marcelo Lubaszewski: Evaluating the effectiveness of a mixed-signal TMR scheme based on design diversity. 134-139
• 
  Jorge Johanny Sáenz Noval, Elkim Felipe Roa Fuentes, Armando Ayala Pabón, Wilhelmus A. M. Van Noije: A methodology to improve yield in analog circuits by using geometric programming. 140-145

Compressed video architectures

• 
  Leonardo Medeiros, Antonio Carlos Cavalcanti: An MPEG-2 transport stream demultiplexer IP corecompliant with SBTVD. 146-150
• 
  Marcel Moscarelli Corrêa, Mateus Thurow Schoenknecht, Luciano Volcan Agostini: A high performance hardware architecture for the H.264/AVC half-pixel motion estimation refinement. 151-156
• 
  Cláudio Machado Diniz, João S. Altermann, Eduardo A. C. da Costa, Sergio Bampi: Performance enhancement of H.264/AVC intra frame prediction hardware using efficient 4-2 and 5-2 adder-compressors. 157-162
• 
  Thaísa Leal da Silva, Luís Alberto da Silva Cruz, Luciano Volcan Agostini: A novel macroblock-level filtering upsampling architecture for H.264/AVC scalable extension. 163-167

Image, video and signal processing

• 
  Alexsandro Cristovão Bonatto, André Borin Soares, Adriano Renner, Altamiro Amadeu Susin, Leandro Max Silva, Sergio Bampi: A 720p H.264/AVC decoder ASIC implementation for digital television set-top boxes. 168-173
• 
  Antonio Lopes Filho, Roberto d'Amore: A low complexity image compression solution for onboard space applications. 174-179
• 
  Angelo G. da Luz, Eduardo A. C. da Costa, Marilton S. de Aguiar: Ordering and partitioning of coefficients based on heuristic algorithms for low power FIR filter realization. 180-185
• 
  Robson Dornelles, Felipe Sampaio, Luciano Volcan Agostini: Variable block size motion estimation architecture with a fast bottom-up decision mode and an integrated motion compensation targeting the H.264/AVC video coding standard. 186-191

Algorithmic advances in CAD

• 
  Felipe S. Marques, Osvaldo Martinello, Renato P. Ribas, André Inácio Reis: Improvements on the detection of false paths by using unateness and satisfiability. 192-197
• 
  Bernardo C. Vieira, Fabrício Vivas Andrade, Antônio Otávio Fernandes: A modular CNF-based SAT solver. 198-203
• 
  Leonardo Londero de Oliveira, João Baptista dos Santos Martins, Gustavo Fernando Dessbesell, José Monteiro: CentroidM: a centroid-based localization algorithm for mobile sensor networks. 204-209
• 
  Gabriel Luca Nazar, Christina Gimmler, Norbert Wehn: Implementation comparisons of the QR decomposition for MIMO detection. 210-214

last updated on Thu May 23 03:40:57 2013 by the dblp team
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