SBCCI 2009: Natal, Brazil

Invited talks

• André Inácio Reis, Roner G. Fabris:
  What about the IP of your IP?: an introduction to intellectual property law for engineers and scientists.
  
• Calvin Plett, Robson Nunes de Lima:
  Low-power CMOS transceivers with on-chip antennas for short-range radio-frequency communication.
  
• M. M. Maharbiz:
  A cyborg beetle: wireless neural flight control of a free-flying insect.
  
• Mohamad Sawan, Benoit Gosselin:
  Multichannel intracortical neurorecording: integration and packaging challenges.
  

Embedded systems

• Chenjie Yu, Xiangrong Zhou, Peter Petrov:
  Low-power inter-core communication through cache partitioning in embedded multiprocessors.
  
• Marcio F. da S. Oliveira, Ronaldo R. Ferreira, Francisco Assis M. do Nascimento, Franz J. Rammig, Flávio Rech Wagner:
  Exploiting the model-driven engineering approach to improve design space exploration of embedded systems.
  
• Abel G. Silva-Filho, C. C. Araújo:
  A methodology for tuning two-level cache hierarchy considering energy and performance.
  
• Luiz Fernando Gonçalves, Jefferson Luiz Bosa, Renato V. B. Henriques, Marcelo Lubaszewski:
  Design of an embedded system for the proactive maintenance of electrical valves.
  

Analog design (1)

• Luciano A. de Lacerda, Edson P. Santana, Cleber Vinícius A. de Almeida, Ana Isabela A. Cunha:
  Distortion analysis of analog multiplier circuits using two-dimensional integral nonlinear function.
  
• André Mansano, Jader A. De Lima, Jacobus Swart:
  A compact fast-response charge-pump gate driver.
  
• Matías R. Miguez, Alfredo Arnaud, Joel Gak:
  A self-protected integrated switch in a HV technology.
  

DSP and arithmetic circuits (1)

• André Silva, Eduardo A. C. da Costa, Sérgio J. M. de Almeida, Marcelo Schiavon Porto, Sergio Bampi:
  High performance motion estimation architecture using efficient adder-compressors.
  
• M. A. Ochoa-Montiel, Bashir M. Al-Hashimi, Peter Kollig:
  Design of a low power MPEG-1 motion vector reconstructor.
  
• Robson Dornelles, Felipe Sampaio, Daniel Palomino, Luciano Volcan Agostini:
  Transforms and quantization design targeting the H.264/AVC intra prediction constraints.
  
• Raju Halder, Parthasarathi Dasgupta, Saptarshi Naskar, Samar Sen-Sarma:
  An internet-based IP protection scheme for circuit designs using linear feedback shift register (LFSR)-based locking.
  

RF design (1)

• Sergio Chaparro, Armando Ayala Pabón, Elkim Roa, Wilhelmus A. M. Van Noije:
  A merged RF CMOS LNA-Mixer design using geometric programming.
  
• Rafaella Fiorelli, Fernando Silveira, Eduardo J. Peralías:
  Phase noise - consumption trade-off in low power RF-LC-VCO design in micro and nanometric technologies.
  
• Laurent Leyssenne, Eric Kerherve, Yann Deval, Didier Belot:
  A novel delta sigma built-in-current-sensor as a signal strength indicator for RF transceiver reconfiguration.
  

Test

• Carlos Ivan Castro Marquez, Marius Strum, Wang Jiang Chau:
  A PD-based methodology to enhance efficiency in testbenches with random stimulation.
  
• Érika F. Cota, Luigi Carro, Felipe Pinto, Ricardo Augusto da Luz Reis, Marcelo Lubaszewski:
  Resource-and-time-aware test strategy for configurable quaternary logic blocks.
  
• Diogo José Costa Alves, Edna Barros:
  A logic built-in self-test architecture that reuses manufacturing compressed scan test patterns.
  
• Wimol San-Um, Masayoshi Tachibana:
  Simultaneous impulse stimulation and response sampling technique for built-in self test of linear analog integrated circuits.
  

Network-on-chip

• Leonel Tedesco, Fabien Clermidy, Fernando Moraes:
  A path-load based adaptive routing algorithm for networks-on-chip.
  
• Sílvio R. F. de Fernandes, Bruno Cruz de Oliveira, Ivan Saraiva Silva:
  Using NoC routers as processing elements.
  
• Marcelo Daniel Berejuck, Cesar Albenes Zeferino:
  Adding mechanisms for QoS to a network-on-chip.
  
• Caroline Concatto, Debora Matos, Luigi Carro, Fernanda Lima Kastensmidt, Altamiro Amadeu Susin, Érika F. Cota, Márcio Eduardo Kreutz:
  Fault tolerant mechanism to improve yield in NoCs using a reconfigurable router.
  

Analog design (2)

• Jader A. De Lima:
  A compact low-distortion low-power instrumentation amplifier.
  
• Juan José Carrillo, Elkim Roa, José Vieira, Wilhelmus A. M. Van Noije:
  A low-voltage bandgap reference source based on the current-mode technique.
  
• Andre Mansano, Andre Vilas Boas, Alfredo Olmos, Jefferson Soldera:
  Zero quiescent current startup circuit with automatic turning-off for low power current and voltage reference.
  
• Genival Mariano de Araujo, Heider Marconi G. Madureira, José Camargo da Costa:
  Design and characterization of a 0.35 micron CMOS voltage-to-current converter.
  

Power dissipation

• Luciano Ost, Guilherme Guindani, Leandro Soares Indrusiak, Cezar Reinbrecht, Thiago Raupp, Fernando Moraes:
  A high abstraction, high accuracy power estimation model for networks-on-chip.
  
• Daniel Schmidt, Norbert Wehn:
  DRAM power management and energy consumption: a critical assessment.
  
• Felipe Klein, Alexandro Baldassin, Guido Araujo, Paulo Centoducatte, Rodolfo Azevedo:
  On the energy-efficiency of software transactional memory.
  

Digital design

• Oliver Sander, Christoph Roth, Vitali Stuckert, Jürgen Becker:
  System concept for an FPGA based real-time capable automotive ECU simulation system.
  
• Igor Dantas dos Santos Miranda, Ana Isabela Araújo Cunha:
  ASIC design of a novel high performance neuroprocessor architecture for multi layered perceptron networks.
  
• Juan Fernando Eusse Giraldo, Michael Hübner, Ricardo Pezzuol Jacobi:
  BRICK: a multi-context expression grained reconfigurable architecture.
  
• Valerij Matrose, Carsten Gremzow:
  Improved placement for hierarchical FPGAs exploiting local interconnect resources.
  

Sensor design

• Frank Sill, Davies W. de Lima Monteiro:
  Pipelined successive approximation conversion (PSAC) with error correction for a CMOS ophthalmic sensor.
  
• Mario Alfredo Reyes-Barranca, Salvador Mendoza-Acevedo, Alejandro Ávila-García, J. L. González-Vidal, Luis M. Flores-Nava:
  Floating gate MOSFET circuit design for a monolithic MEMS GAS sensor.
  

DSP and arithmetic circuits (2)

• Diego F. Sánchez, Daniel M. Muñoz, Carlos H. Llanos, Mauricio Ayala-Rincón:
  Parameterizable floating-point library for arithmetic operations in FPGAs.
  
• Thaísa Leal da Silva, Fabio Pereira, Altamiro Amadeu Susin, Sergio Bampi, Luciano Volcan Agostini:
  High performance and low cost architecture for H.264/AVC CAVLD targeting HDTV.
  
• Viviane Lucy Santos de Souza, Victor Wanderley Costa Medeiros, Manoel Eusebio de Lima:
  Architecture for dense matrix multiplication on a high-performance reconfigurable system.
  
• Levent Aksoy, Diego Jaccottet, Eduardo Costa:
  Design of low complexity digital FIR filters.
  

RF design (2)

• Cédric Majek, Yann Deval, Hervé Lapuyade, Jean-Baptiste Begueret:
  Voltage controlled delay line with phase quadrature outputs for [0.9-4] GHz F-DLL dedicated to zero-IF multi-standard LO.
  
• Antonio Felipe de Freitas Silva, Fernando Rangel de Sousa:
  Highly improved IIP2 direct conversion receiver.
  
• Luiz Carlos Moreira, Wilhelmus A. M. Van Noije, Armando Ayala Pabón, Andrés Farfán-Peláez:
  Comparison of small cross inductors and rectangular inductors designed in 0.35um CMOS technology.
  
• M. J. Uddin, Muhammad I. Ibrahimy, M. A. Hasan, Mohd. Alauddin Mohd. Ali, Mamun Bin Ibne Reaz:
  CMOS 2.45GHz RF power amplifier for RFID reader.
  

Reliability

• Costas Argyrides, Giorgos Dimosthenous, Dhiraj K. Pradhan, Carlos Arthur Lang Lisbôa, Luigi Carro:
  Reliability aware yield improvement technique for nanotechnology based circuits.
  
• Gustavo Neuberger, Gilson I. Wirth, Ricardo Reis:
  Protecting digital circuits against hold time violation due to process variability.
  
• Hagen Sämrow, Claas Cornelius, Frank Sill, Andreas Tockhorn, Dirk Timmermann:
  Twin logic gates: improved logic reliability by redundancy concerning gate oxide breakdown.
  

Verification

• Francisco Assis M. do Nascimento, Marcio F. da S. Oliveira, Flávio Rech Wagner:
  Using MDE for the formal verification of embedded systems modeled by UML sequence diagrams.
  
• George Sobral Silveira, Alisson Vasconcelos De Brito, Elmar U. K. Melcher:
  Functional verification of power gate design in SystemC RTL.
  
• Danilo Ravotto, Edgar E. Sánchez, Matteo Sonza Reorda, Giovanni Squillero:
  Design validation of multithreaded architectures using concurrent threads evolution.
  
• Emilio Wuerges, Luiz C. V. dos Santos, Olinto J. V. Furtado, Sandro Rigo:
  An early real-time checker for retargetable compile-time analysis.
  

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