SBCCI 2006: Ouro Preto, MG, Brazil

Tutorials

• Michael Hübner, Jürgen Becker:
  Exploiting dynamic and partial reconfiguration for FPGAs: toolflow, architecture and system integration. 1-4
  
• Valeria Bertacco:
  Formal verification for real-world designs. 5
  
• Todd M. Austin:
  Robust low power computing in the nanoscale era. 6
  
• Reiner W. Hartenstein:
  The re-definition of low power design for HPC: a paradigm shift. 7
  
• Andrès E. Lagos:
  High performance silicon MEMS for niche market applications. 8
  
• Jürgen Becker, Michael Hübner:
  Run-time reconfigurabilility and other future trends. 9-11
  
• Valeria Bertacco:
  Low maintenance verification. 12
  
• Todd M. Austin:
  Razor: a low-power pipeline based on circuit-level timing speculation. 13
  

Reconfigurable architectures

• Victor M. Goulart Ferreira, Lovic Gauthier, Takayuki Kando, Takuma Matsuo, Toshihiko Hashinaga, Kazuaki Murakami:
  REDEFIS: a system with a redefinable instruction set processor. 14-19
  
• R. U. R. Mocho, G. H. Sartori, Renato P. Ribas, André Inácio Reis:
  Asynchronous circuit design on reconfigurable devices. 20-25
  
• Jozias Oliveira, André Printes, R. C. S. Freire, Elmar U. K. Melcher, Ivan S. S. Silva:
  FPGA architecture for static background subtraction in real time. 26-31
  
• Daniel M. Muñoz, Carlos H. Llanos, Mauricio Ayala-Rincón, Rudi H. van Els, Renato P. Almeida:
  Implementation of dispatching algorithms for elevator systems using reconfigurable architectures. 32-37
  

Dynamic reconfiguration

• Thilo Streichert, Christian Strengert, Christian Haubelt, Jürgen Teich:
  Dynamic task binding for hardware/software reconfigurable networks. 38-43
  
• Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes:
  Infrastructure for dynamic reconfigurable systems: choices and trade-offs. 44-49
  
• Paulo Sérgio B. do Nascimento, Manoel Eusebio de Lima, Stelita M. da Silva, Jordana L. Seixas:
  Mapping of image processing systems to FPGA computer based on temporal partitioning and design space exploration. 50-55
  

Network on chip

• Masoud Daneshtalab, Ali Afzali-Kusha, Ashkan Sobhani, Zainalabedin Navabi, Mohammad D. Mottaghi, Omid Fatemi:
  Ant colony based routing architecture for minimizing hot spots in NOCs. 56-61
  
• Leonel Tedesco, Aline Mello, Leonardo Giacomet, Ney Calazans, Fernando Gehm Moraes:
  Application driven traffic modeling for NoCs. 62-67
  
• Mário P. Véstias, Horácio C. Neto:
  Area and performance optimization of a generic network-on-chip architecture. 68-73
  

Low power and analog design

• Sandro A. P. Haddad, Wouter A. Serdijn:
  An ultra low-power class-AB sinh integrator. 74-79
  
• Luis H. C. Ferreira, Tales Cleber Pimenta, Robson L. Moreno, Wilhelmus A. M. Van Noije:
  Ultra low-voltage ultra low-power CMOS threshold voltage reference. 80-82
  
• Hamilton Klimach, Márcio C. Schneider, Carlos Galup-Montoro:
  A test chip for automatic MOSFET mismatch characterization. 83-88
  
• Alessandro Girardi, Sergio Bampi:
  Power constrained design optimization of analog circuits based on physical gm/ID characteristics. 89-93
  

Analog and mixed signal design

• Pablo Aguirre, Fernando Silveira:
  Bias circuit design for low-voltage cascode transistors. 94-97
  
• Fabio Lacerda, Stefano Pietri, Alfredo Olmos:
  A differential switched-capacitor amplifier with programmable gain and output offset voltage. 98-102
  
• A. A. Mariano, Dominique Dallet, Yann Deval, Jean-Baptiste Begueret:
  4GHz continuous-time bandpass delta-sigma modulator for directly high IF A/D conversion. 103-107
  
• Ana Isabela Araújo Cunha, Ali M. Niknejad:
  A general domain CMOS companding integrator. 108-112
  

Modeling, synthesis and formal verification

• Heiner Giefers, Achim Rettberg:
  Energy aware multiple clock domain scheduling for a bit-serial, self-timed architecture. 113-118
  
• David Déharbe, Sergio Medeiros:
  Aspect-oriented design in systemC: implementation and applications. 119-124
  
• Mauricio Ayala-Rincón, Thomas Mailleux Santana:
  SAEPTUM: verification of ELAN hardware specifications using the proof assistant PVS. 125-130
  
• Romanelli Lodron Zuim, José T. de Sousa, Claudionor José Nunes Coelho Jr.:
  A fast SAT solver algorithm best suited to reconfigurable hardware. 131-136
  
• Leomar S. da Rosa Jr., Felipe S. Marques, Tiago Muller Gil Cardoso, Renato P. Ribas, Sachin S. Sapatnekar, André Inácio Reis:
  Fast disjoint transistor networks from BDDs. 137-142
  

Embedded systems

• Francisco Assis M. do Nascimento, Marcio F. da S. Oliveira, Marco A. Wehrmeister, Carlos Eduardo Pereira, Flávio Rech Wagner:
  MDA-based approach for embedded software generation from a UML/MOF repository. 143-148
  
• Elias Teodoro Silva Jr., Flávio Rech Wagner, Edison Pignaton de Freitas, Carlos Eduardo Pereira:
  Hardware support in a middleware for distributed and real-time embedded applications. 149-154
  
• Antonio Carlos Schneider Beck, Mateus B. Rutzig, Luigi Carro:
  Cache performance impacts for stack machines in embedded systems. 155-160
  

Digital and low power design

• Eduardo A. C. da Costa, Paulo F. Flores, José Monteiro:
  Exploiting general coefficient representation for the optimal sharing of partial products in MCMs. 161-166
  
• Ricardo C. Goncalves da Silva, Henri Boudinov, Luigi Carro:
  A cell library for low power high performance CMOS voltage-mode quaternary logic. 167-172
  
• Katarina Paulsson, Michael Hübner, Jürgen Becker:
  On-line optimization of FPGA power-dissipation by exploiting run-time adaption of communication primitives. 173-178
  
• Mohammad D. Mottaghi, Ali Afzali-Kusha, Zainalabedin Navabi:
  ByZFAD: a low switching activity architecture for shift-and-add multipliers. 179-183
  

Test and verification

• Gilson I. Wirth, Ivandro Ribeiro, Michele G. Vieira, Fernanda Gusmão de Lima Kastensmidt:
  Single event transients in dynamic logic. 184-189
  
• Carlos Roberto Moratelli, Érika F. Cota, Marcelo Lubaszewski:
  A cryptography core tolerant to DFA fault attacks. 190-195
  
• Rodrigo Possamai Bastos, Fernanda Lima Kastensmidt, Ricardo Reis:
  Design at high level of a robust 8-bit microprocessor to soft errors by using only standard gates. 196-201
  
• Arthur Pereira Frantz, Fernanda Lima Kastensmidt, Luigi Carro, Érika F. Cota:
  Evaluation of SEU and crosstalk effects in network-on-chip switches. 202-207
  
• Margrit R. Krug, Marcelo de Souza Moraes, Marcelo Lubaszewski:
  Using a software testing technique to identify registers for partial scan implementation. 208-213
  
• André V. Fidalgo, Manuel G. Gericota, Gustavo R. Alves, José M. Ferreira:
  Using NEXUS compliant debuggers for real time fault injection on microprocessors. 214-219
  

Physical and analog design

• Renato Fernandes Hentschke, Guilherme Flach, Felipe Pinto, Ricardo Reis:
  Quadratic placement for 3d circuits using z-cell shifting, 3d iterative refinement and simulated annealing. 220-225
  
• Daniele Bonomi, Giorgio Boselli, Gabriella Trucco, Valentino Liberali:
  Effects of digital switching noise on analog voltage references in mixed-signal CMOS ICs. 226-231
  
• Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi:
  A band-pass Gm-C Filter design based on gm/ID methodology and characterization. 232-237
  

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