SBCCI 2003: Sao Paulo, Brazil

Tutorials

• Grant Martin:
  SystemC: From Language to Applications, from Tools to Methodologies. 3
  
• Patrick Lysaght:
  System-Level Design for FPGAs. 4
  
• Luiz Franca-Neto:
  High-Performance RF/Microwave Integrated Circuits in Advanced Logic CMOS Technology: The Coming of Age for RF/Digital Mixed-Signal System-on-a-Package. 5
  

Advanced Amplifier Design

• Julio Arlindo Pinto Azevedo, Tales Cleber Pimenta:
  Design of a Low Noise Amplifier for CDMA Transceivers at 900MHz in CMOS 0.35 µm. 9-13
  
• Elkim Roa, Joao Navarro Soares, Wilhelmus A. M. Van Noije:
  A Methodology for CMOS Low Noise Ampli.er Design. 14-19
  
• Pablo Aguirre, Fernando Silveira:
  Design of a Reusable Rail-to-Rail Operational Amplifier. 20-25
  
• Salvador Pinillos Gimenez, Marcelo Antonio Pavanello, João Antonio Martino, S. Adriaensen, Denis Flandre:
  Design of Operational Transconductance Amplifiers with Improved Gain by Using Graded-Channel SOI nMOSFETs. 26-
  

Logic Synthesis Techniques

• Maurizio Damiani, Andrei Y. Selchenko:
  Boolean Technology Mapping Based on Logic Decomposition. 35-40
  
• Ivan Augé, François Donnet, Frédéric Pétrot:
  Retiming Finite State Machines to Control Hardened Data-Paths. 41-46
  
• Luca P. Carloni, Alberto L. Sangiovanni-Vincentelli:
  Combining Retiming and Recycling to Optimize the Performance of Synchronous Circuits. 47-52
  
• Dmitri Maslov, Gerhard W. Dueck, D. Michael Miller:
  Simplification of Toffoli Networks via Templates. 53-
  

Invited Paper

• Grant Martin:
  SystemC and the Future of Design Languages: Opportunities for Users and Research. 61
  

Digital Design Techniques

• Eduardo A. C. da Costa, Sergio Bampi, José C. Monteiro:
  A New Pipelined Array Architecture for Signed Multiplication. 65-70
  
• Sumeer Goel, Mohamed A. Elgamel, Magdy A. Bayoumi:
  Novel Design Methodology for High-Performance XOR-XNOR Circuit Design. 71-
  

High-Level and Co-Design Approaches

• Achim Rettberg, Florian Dittmann, Mauro Cesar Zanella, Thomas Lehmann:
  Towards a High-Level Synthesis of Reconfigurable Bit-Serial Architectures. 79-84
  
• Mário P. Véstias, Horácio C. Neto:
  DALI: A Methodology for the Co-Design of Dataflow Applications on Hardware/Software Architectures. 85-
  

Mapping Applications onto FPGAs

• Diogo Zandonai, Sergio Bampi, Marcel Bergerman:
  ME64 - A Highly Scalable Hardware Parallel Architecture Motion Estimation in FPGA. 93-98
  
• Abel Guilhermino S. Filho, Alejandro César Frery, Cristiano C. de Araujo, Haglay Alice, Jorge Cerqueira, Juliana A. Loureiro, Manoel Eusebio de Lima, Maria das Gracas S. Oliveira, Michelle Matos Horta:
  Hyperspectral Images Clustering on Reconfigurable Hardware Using the K-Means Algorithm. 99-104
  
• Sandro Ferreira, Felipe Haffner, Luis Fernando Pereira, Fernando Moraes:
  Design and Prototyping of Direct Torque Control of Induction Motors in FPGAs. 105-110
  
• Nadia Nedjah, Luiza de Macedo Mourelle:
  FPGA-Based Hardware Architecture for Neural Networks: Binary Radix vs. Stochastic. 111-
  

IP Integration Techniques

• Markus Visarius, Johannes Lessmann, Wolfram Hardt, Frank Kelso, Wolfgang Thronicke:
  An XML Format Based Integration Infrastructure for IP Based Design. 119-124
  
• Uilian Rafael Feijo Souza, Josue Klafke Sperb, Braulio Adriano de Mello, Flávio Rech Wagner:
  Tangram - Virtual Integration of Heterogeneous IP Components in a Distributed Co-Simulation Environment. 125-130
  
• Julio A. de Oliveira Filho, Manoel Eusebio de Lima, Paulo Romero Martins Maciel, Juliana Moura, Bruno Celso:
  A Fast IP-Core Integration Methodology for SoC Design. 131-136
  
• Eric E. Fabris, Luigi Carro, Sergio Bampi:
  A Universal High-Performance Analog Interface for Signal Processing SOCs. 137-
  

Invited Paper

• Santanu Dutta:
  Architecture and Implementation of Multi-Processor SoCs for Advanced Set-Top Box and Digital TV Systems. 145
  

Asynchronous Design Techniques

• João Leonardo Fragoso, Gilles Sicard, Marc Renaudin:
  Automatic Generation of 1-of-M QDI Asynchronous Adders. 149-154
  
• Artur Pereira, Antonio Rui Borges, Antonio Ferrari:
  Exclusion Relation of k Out of n and the Synthesis of Speed-Independent Circuits. 155-
  

Networks-on-Chip

• Tang Lei, Shashi Kumar:
  Algorithms and Tools for Network on Chip Based System Design. 163-168
  
• Cesar Albenes Zeferino, Altamiro Amadeu Susin:
  SoCIN: A Parametric and Scalable Network-on-Chip. 169-
  

Application Specific RF and Analog Design

• Jefferson B. D. Soldera, Andre Vilas Boas, Alfredo Olmos:
  A Low Ripple Fully Integrated Charge Pump Regulator. 177-180
  
• Alfredo Olmos:
  A Temperature Compensated Fully Trimmable On-Chip IC Oscillator. 181-186
  
• Fernando C. Castaldo, Joao Paulo C. Cajueiro, Carlos Alberto dos Reis:
  Bias Dependence of Noise Correlation in MAGFETs. 187-190
  
• Esther Rodríguez-Villegas, Alberto Yufera, Adoración Rueda:
  A Charge Correction Cell for FGMOS-Based Circuits. 191-
  

Applications of Formal Methods to Design

• Renato E. B. Poli, Felipe Ribeiro Schneider, Renato P. Ribas, André Inácio Reis:
  Unified Theory to Build Cell-Level Transistor Networks from BDDs. 199-204
  
• Mauricio Ayala-Rincón, Rodrigo B. Nogueira, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein:
  Modeling a Reconfigurable System for Computing the FFT in Place via Rewriting-Logic. 205-210
  
• George Logothetis, Klaus Schneider, C. Metzler:
  Runtime Analysis of Synchronous Programs for Low-Level Real-Time Verification. 211-216
  
• Geert Janssen:
  A Consumer Report on BDD Packages. 217-
  

Novel Architectures

• Arnaldo Azevedo, Rodrigo Soares, Ivan Saraiva Silva:
  A New Hybrid Parallel/Reconfigurable Architecture: The X4CP32. 225-230
  
• Achim Rettberg, Mauro Cesar Zanella, Thomas Lehmann, Ulrich Dierkes, Carsten Rustemeier:
  Control Development for Mechatronic Systems with a Fully Reconfigurable Pipeline Architecture. 231-236
  
• Jürgen Becker, Alexander Thomas, Maik Scheer:
  Efficient Processor Instruction Set Extension by Asynchronous Reconfigurable Datapath Integration. 237-242
  
• Ryuichi Takahashi, Hajime Ohiwa:
  Situated Learning on FPGA for Superscalar Microprocessor Design Education. 243-
  

Noise Analysis and Layout

• Howard H. Chen, J. Scott Neely, Michael F. Wang, Gricel Co:
  On-Chip Decoupling Capacitor Optimization for Noise and Leakage Reduction. 251-255
  
• Mohamed A. Elgamel, Magdy A. Bayoumi:
  Minimum-Area Shield Insertion for Explicit Inductive Noise Reduction. 256-260
  
• Janet Meiling Wang, Pinhong Chen, Omar Hafiz:
  A New Continuous Switching Window Computation with Crosstalk Noise. 261-266
  
• Renato Fernandes Hentschke, Ricardo Augusto da Luz Reis:
  Improving Simulated Annealing Placement by Applying Random and Greedy Mixed Perturbations. 267-
  

Invited Paper

• Patrick Lysaght:
  Future Design Tools for Platform FPGAs. 275-
  

Issues in Reconfigurable Architectures

• Jürgen Becker, Michael Hübner, Michael Ullmann:
  Power Estimation and Power Measurement of Xilinx Virtex FPGAs: Trade-Offs and Limitations. 283-288
  
• Romanelli Lodron Zuim, Claudionor José Nunes Coelho Jr., Luiz Fernando Etrusco Moreira, Antônio Otávio Fernandes, José Monteiro da Mata, Diógenes Cecilio da Silva Jr.:
  Dynamic Reconfiguration Behavior Using Generic FPGAs and FPIDs. 289-
  

Timing Analysis and Layout

• Daniel Lima Ferrão, Gustavo Wilke, Ricardo Augusto da Luz Reis, José Luís Almada Güntzel:
  Improving Critical Path Identification in Functional Timing Analysis. 297-302
  
• Cristiano Santos, Gustavo Wilke, Cristiano Lazzari, Ricardo Reis, José Luís Almada Güntzel:
  A Transistor Sizing Method Applied to an Automatic Layout Generation Tool. 303-
  

Innovative Approaches to RF and Analog Design Problems

• Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eric E. Fabris, Sergio Bampi:
  Analog IC Modules Design Using Trapezoidal Association of MOS Transistors in 0.35µm Technology. 311-316
  
• Antonio J. Ginés, Eduardo J. Peralías, Adoración Rueda:
  Digital Background Calibration Technique for Pipeline ADCs with Multi-Bit Stages. 317-322
  
• Faress Tissafi-Drissi, Ian O'Connor, Fabien Mieyeville, Frédéric Gaffiot:
  Design Methodologies for High-Speed CMOS Photoreceiver Front-Ends. 323-328
  
• Marcelo Negreiros, Erik Schüler, Luigi Carro, Altamiro Amadeu Susin:
  Testing RF Signal Paths Using Spectral Analysis and Subsampling. 329-
  

High-Level Validation and Modeling

• J. Pérez, Matteo Sonza Reorda, Massimo Violante:
  Accurate Dependability Analysis of CAN-Based Networked Systems. 337-342
  
• Christian Haubelt, Dirk Koch, Jürgen Teich:
  ReCoNet: Modeling and Implementation of Fault Tolerant Distributed Reconfigurable Hardware. 343-348
  
• Antonio C. S. Beck Filho, Júlio C. B. de Mattos, Flávio Rech Wagner, Luigi Carro:
  CACO-PS: A General Purpose Cycle-Accurate Configurable Power Simulator. 349-354
  
• Ney Laert Vilar Calazans, Edson I. Moreno, Fabiano Hessel, Vitor M. da Rosa, Fernando Moraes, Everton Carara:
  From VHDL Register Transfer Level to SystemC Transaction Level Modeling: A Comparative Case Study. 355-
  

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