Power and Energy Efficiency

• 
  Timothy N. Miller, Nagarjuna Surapaneni, Radu Teodorescu: Flexible Error Protection for Energy Efficient Reliable Architectures. 1-8
• 
  Epifanio Gaona-Ramírez, J. Rubén Titos Gil, Juan Fernández, Manuel E. Acacio: Characterizing Energy Consumption in Hardware Transactional Memory Systems. 9-16
• 
  Muhammad Ali Shami, Ahmed Hemani: Control Scheme for a CGRA. 17-24
• 
  Tushar Gupta, Clement Bertolini, Olivier Héron, Nicolas Ventroux, Thomas Zimmer, François Marc: High Level Power and Energy Exploration Using ArchC. 25-32

Programming with GPUs, FPGAs and Other Accelerator Architectures

• 
  Bruno Coutinho, Diogo Sampaio, Fernando Magno Quintão Pereira, Wagner Meira Jr.: Performance Debugging of GPGPU Applications with the Divergence Map. 33-40
• 
  Mujahed Eleyat, Lasse Natvig: Mixed-Precision Parallel Linear Programming Solver. 41-46
• 
  George Teodoro, Nathan Mariano, Wagner Meira Jr., Renato Ferreira: Tree Projection-Based Frequent Itemset Mining on Multicore CPUs and GPUs. 47-54

Load Balancing and Scheduling

• 
  Anne Benoit, Loris Marchal, Yves Robert, Oliver Sinnen: Mapping Pipelined Applications with Replication to Increase Throughput and Reliability. 55-62
• 
  Hong Min, Hubertus Franke: Improving In-memory Column-Store Database Predicate Evaluation Performance on Multi-core Systems. 63-70
• 
  Eduardo Rocha Rodrigues, Philippe Olivier Alexandre Navaux, Jairo Panetta, Alvaro Luiz Fazenda, Celso L. Mendes, Laxmikant V. Kalé: A Comparative Analysis of Load Balancing Algorithms Applied to a Weather Forecast Model. 71-78
• 
  Anne Benoit, Paul Renaud-Goud, Yves Robert: Sharing Resources for Performance and Energy Optimization of Concurrent Streaming Applications. 79-86

Cache Design and Performance Analysis

• 
  Sandro Bartolini, Pierfrancesco Foglia, Marco Solinas, Cosimo Antonio Prete: Feedback-Driven Restructuring of Multi-threaded Applications for NUCA Cache Performance in CMPs. 87-94
• 
  Xi Zhang, Chongmin Li, Haixia Wang, Dongsheng Wang: A Cache Replacement Policy Using Adaptive Insertion and Re-reference Prediction. 95-102
• 
  Filipe R. Cordeiro, Abel G. Silva-Filho, G. R. Carvalho: MOPSO Applied to Architecture Tuning with Unified Second-Level Cache for Energy and Performance Optimization. 103-110
• 
  Felipe Pedroni, Alberto Ferreira de Souza, Claudine Badue: The Dynamic Block Remapping Cache. 111-118

Grid and Peer-to-Peer Systems

• 
  Iván Cores, Gabriel Rodríguez, María J. Martín, Patricia González: Achieving Fault Tolerance on Grids with the CPPC Framework and the GridWay Metascheduler. 119-126
• 
  Luciano José, Senger Márcio Augusto de Souza, Dierone Cesar Foltran Jr.: Towards a Peer-to-Peer Framework for Parallel and Distributed Computing. 127-134
• 
  Eduardo C. Xavier, Robson R. S. Peixoto: On the Worst Case of Scheduling with Task Replication on Computational Grids. 135-142

Parallel Algorithms and Applications

• 
  Yinglong Xia, Viktor K. Prasanna: Distributed Evidence Propagation in Junction Trees. 143-150
• 
  Jose J. Camata, Alvaro L. G. A. Coutinho: Parallel Linear Octree Meshing with Immersed Surfaces. 151-158
• 
  Pascal Vezolle, Jerry Heyman, Bruce D'Amora, Gordon W. Braudaway, Karen A. Magerlein, John Magerlein, Yvan Fournier: Accelerating Computational Fluid Dynamics on the IBM Blue Gene/P Supercomputer. 159-166
• 
  Ricardo M. Czekster, Paulo Fernandes, Afonso Sales, Thais Webber: Performance Issues for Parallel Implementations of Bootstrap Simulation Algorithm. 167-174

Modeling, Benchmarking and Performance Evaluation

• 
  Xiao Yu, Zhengyu He, Bo Hong: An Analytical Model on the Execution of Transactional Memory. 175-182
• 
  Pilar Gonzalez-Ferez, Juan Piernas, Toni Cortes: Simultaneous Evaluation of Multiple I/O Strategies. 183-190
• 
  Antonio García-Guirado, Ricardo Fernández Pascual, José M. García: Analyzing Cache Coherence Protocols for Server Consolidation. 191-198
• 
  Rodrigo Virote Kassick, Francieli Zanon Boito, Philippe Olivier Alexandre Navaux: Impact of I/O Coordination on a NFS-Based Parallel File System with Dynamic Reconfiguration. 199-206

Tools and Strategies for Parallel and Distributed Programming

• 
  Terry Jones, Gregory A. Koenig: A Clock Synchronization Strategy for Minimizing Clock Variance at Runtime in High-End Computing Environments. 207-214
• 
  Thomas Preud'homme, Julien Sopena, Gaël Thomas, Bertil Folliot: BatchQueue: Fast and Memory-Thrifty Core to Core Communication. 215-222
• 
  Ricardo Nabinger Sanchez, José Nelson Amaral, Duane Szafron, Marius Pirvu, Mark G. Stoodley: Using Support Vector Machines to Learn How to Compile a Method. 223-230
• 
  Jan Hendrik Schönherr, Jan Richling, Hans-Ulrich Heiss: Dynamic Teams in OpenMP. 231-237

last updated on Sat May 18 05:31:57 2013 by the dblp team
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