7. SASP 2009:
San Francisco,
California,
USA
Proceedings of the IEEE 7th Symposium on Application Specific Processors, SASP 2009, San Francisco, CA, USA , July 27-28, 2009.
IEEE Computer Society 2009, ISBN 978-1-4244-4939-2 
- Wei Han, Ying Yi, Xin Zhao, Mark Muir, Tughrul Arslan, Ahmet T. Erdogan:
Heterogeneous multi-core architectures with dynamically reconfigurable processors for wireless communication.
1-6
- Shoaib Akram, Rakesh Kumar, Deming Chen:
Workload adaptive shared memory multicore processors with reconfigurable interconnects.
7-14
- Hyunchul Park, Yongjun Park, Scott A. Mahlke:
A dataflow-centric approach to design low power control paths in CGRAs.
15-20
- Giovanni Mariani, Gianluca Palermo, Cristina Silvano, Vittorio Zaccaria:
A design space exploration methodology supporting run-time resource management for multi-processor Systems-on-chip.
21-28
- Ganesh S. Dasika, Kevin Fan, Scott A. Mahlke:
Power-efficient medical image processing using PUMA.
29-34
- Alexandros Papakonstantinou, Karthik Gururaj, John A. Stratton, Deming Chen, Jason Cong, Wen-mei W. Hwu:
FCUDA: Enabling efficient compilation of CUDA kernels onto FPGAs.
35-42
- Maryam Moazeni, Alex A. T. Bui, Majid Sarrafzadeh:
A memory optimization technique for software-managed scratchpad memory in GPUs.
43-49
- Nam Duong, Rakesh Kumar:
Register Multimapping: A technique for reducing register bank conflicts in processors with large register files.
50-53
- Ajay K. Verma, Yi Zhu, Philip Brisk, Paolo Ienne:
Arithmetic optimization for custom instruction set synthesis.
54-57
- Jonghee M. Youn, Minwook Ahn, Daeho Kim, Jonghee W. Yoon, Yunheung Paek, Sechul Shin, Hochang Chae, Jeonghun Cho:
A new addressing mode for the encoding space problem on embedded processors.
58-61
- Jehangir Khan, Smaïl Niar, Mazen A. R. Saghir, Yassin Elhillali, Atika Rivenq:
Driver assistance system design and its optimization for FPGA based MPSoC.
62-65
- Junguk Cho, Bridget Benson, Ryan Kastner:
Hardware acceleration of multi-view face detection.
66-69
- Bo Zhou, Xiaobo Sharon Hu, Danny Z. Chen, Cedric X. Yu:
A multi-FPGA accelerator for radiation dose calculation in cancer treatment.
70-79
- Dimitris Theodoropoulos, Georgi Kuzmanov, Georgi Gaydadjiev:
A reconfigurable beamformer for audio applications.
80-87
- Amin Ansari, Dan Zhang, Scott A. Mahlke:
Parade: A versatile parallel architecture for accelerating pulse train clustering.
88-93
- Cheng Ling, Khaled Benkrid, Tsuyoshi Hamada:
A parameterisable and scalable Smith-Waterman algorithm implementation on CUDA-compatible GPUs.
94-100
- Mathew Paul, Peter Petrov:
Dynamic and application-driven I-cache partitioning for low-power embedded multitasking.
101-106
- Yuanrui Zhang, Mahmut T. Kandemir:
A hardware-software codesign strategy for Loop intensive applications.
107-113
- Marcela Zuluaga, Theo Kluter, Philip Brisk, Nigel P. Topham, Paolo Ienne:
Introducing control-flow inclusion to support pipelining in custom instruction set extensions.
114-121
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