16. RSP 2005: Montreal, Canada

Introduction

• Message from the General Chairs.
  
• Message from the Organizing Chair.
  
• Message from the Program Chairs.
  
• Conference Committees.
  

Networks and Protocols

• Stefan Ihmor, Tobias Loke, Wolfram Hardt:
  Synthesis of Communication Structures and Protocols in Distributed Embedded Systems. 3-9
  
• Matthieu Briere, Emmanuel Drouard, Fabien Mieyeville, David Navarro, Ian O'Connor, Frédéric Gaffiot:
  Heterogeneous Modelling of an Optical Network-on-Chip with SystemC. 10-16
  
• César A. M. Marcon, Márcio Eduardo Kreutz, Altamiro Amadeu Susin, Ney Laert Vilar Calazans:
  Models for Embedded Application Mapping onto NoCs: Timing Analysis. 17-23
  
• Romain Lemaire, Fabien Clermidy, Y. Durand, Didier Lattard, Ahmed Amine Jerraya:
  Performance Evaluation of a NoC-Based Design for MC-CDMA Telecommunications Using NS-2. 24-30
  

Tools for Rapid Prototyping

• James Lapalme, El Mostapha Aboulhamid, Gabriela Nicolescu:
  Leveraging Model Representations for System Level Design Tools. 33-39
  
• Chia-Jui Hsu, Shuvra S. Bhattacharyya:
  Porting DSP Applications across Design Tools Using the Dataflow Interchange Format. 40-46
  
• Arnaud Grasset, Frédéric Rousseau, Ahmed Amine Jerraya:
  Automatic Generation of Component Wrappers by Composition of Hardware Library Elements Starting from Communication Service Specification. 47-53
  
• Etienne Bergeron, Xavier Saint-Mleux, Marc Feeley, Jean-Pierre David:
  High Level Synthesis for Data-Driven Applications. 54-60
  

FPGAs for Rapid Prototyping

• Mehrdad Najibi, Kamran Saleh, Mohsen Naderi, Hossein Pedram, Mehdi Sedighi:
  Prototyping Globally Asynchronous Locally Synchronous Circuits on Commercial Synchronous FPGAs. 63-69
  
• Markus Visarius, André Meisel, Markus Scheithauer, Wolfram Hardt:
  Dynamic Reconfiguration of IP-Based Systems. 70-76
  
• Yana Esteves Krasteva, Ana B. Jimeno, Eduardo de la Torre, Teresa Riesgo:
  Straight Method for Reallocation of Complex Cores by Dynamic Reconfiguration in Virtex II FPGAs. 77-83
  
• Ali Ahmadinia, Christophe Bobda, Ji Ding, Mateusz Majer, Jürgen Teich, Sándor P. Fekete, Jan van der Veen:
  A Practical Approach for Circuit Routing on Dynamic Reconfigurable Devices. 84-90
  

Software Design and Prototyping

• Ghulam Qader, M. Younus Javed:
  Simulation of Resolution of CS Problem for Multiple Common Variables in Multiprocessor Environment. 93-98
  
• John D. Carter, Ming Xu, William B. Gardner:
  Rapid Prototyping of Embedded Software Using Selective Formalism. 99-104
  
• Doron Drusinsky, Man-tak Shing, Kadir Alpaslan Demir:
  Test-Time, Run-Time, and Simulation-Time Temporal Assertions in RSP. 105-110
  
• Thomas Vergnaud, Jérôme Hugues, Laurent Pautet, Fabrice Kordon:
  Rapid Development Methodology for Customized Middleware. 111-117
  

Applications

• Deepak Argarwal, Christopher Robert Anderson, Peter M. Athanas:
  An 8-GHz Ultra Wideband Transceiver Prototyping Testbed. 121-127
  
• Ben Cordes, Jennifer G. Dy, Miriam Leeser, James Goebel:
  Enabling a Real-Time Solution for Neuron Detection with Reconfigurable Hardware. 128-134
  
• Carsten Bieser, Klaus D. Müller-Glaser:
  COMPASS - A Novel Concept of a Reconfigurable Platform for Automotive System Development and Test. 135-140
  
• Benny Thörnberg, Leif Olsson, Mattias O'Nils:
  Optimization of Memory Allocation for Real-Time Video Processing on FPGA. 141-147
  

Processor Design and Prototyping

• Kugan Vivekanandarajah, Thambipillai Srikanthan:
  Custom Instruction Filter Cache Synthesis for Low-Power Embedded Systems. 151-157
  
• Moo-Kyoung Chung, Heejun Shim, Chong-Min Kyung:
  Performance Improvement of Multiprocessor Simulation by Optimizing Synchronization a Communication. 158-164
  
• Oliver Schliebusch, Anupam Chattopadhyay, Ernst Martin Witte, David Kammler, Gerd Ascheid, Rainer Leupers, Heinrich Meyr:
  Optimization Techniques for ADL-Driven RTL Processor Synthesis. 165-171
  
• Pavle Belanovic, Markus Rupp:
  Automated Floating-Point to Fixed-Point Conversion with the Fixify Environment. 172-178
  

Testing Issues in Prototyping

• Faouzi Bouchhima, Gabriela Nicolescu, El Mostapha Aboulhamid, Mohamed Abid:
  Discrete-Continuous Simulation Model for Accurate Validation in Component-Based Heterogeneous SoC Design. 181-187
  
• Mikhail Auguston, James Bret Michael, Man-tak Shing:
  Test Automation and Safety Assessment in Rapid Systems Prototyping. 188-194
  
• Levi Lucio, Luis Pedro, Didier Buchs:
  A Test Language for CO-OPN Specifications. 195-201
  
• Chadlia Jerad, Kamel Barkaoui:
  On the Use of Rewriting Logic for Verification of Distributed Software Architecture Description Based LfP. 202-208
  

Co-Design I

• Silvio Dragone, Clemens Lombriser:
  The Ordering of Events in a Prototyping Platform. 211-217
  
• Ivan Petkov, Paul Amblard, Marin Hristov:
  Systematic Design Flow for Fast Hardware/Software Prototype Generation from Bus Functional Model for MPSoC. 218-224
  
• Leandro Soares Indrusiak, Romualdo Begale Prudencio, Manfred Glesner:
  Modeling and Prototyping of Communication Systems Using Java: A Case Study. 225-231
  
• Martin Irman, Jan Bajcsy:
  A Rapid System Prototyping Platform for Error Control Coding in Optical CDMA Networks. 232-234
  

Co-Design II

• Sanggyu Park, Soo-Ik Chae:
  A C/C++-Based Functional Verification Framework Using the SystemC Verification Library. 237-239
  
• Sylvain Huet, Emmanuel Casseau, Olivier Pasquier:
  Design Exploration and HW/SW Rapid Prototyping for Real-Time System Design. 240-243
  
• Luke Demoracski, Dimiter R. Avresky:
  An Approach for Functional Decomposition Applied to State-Based Designs. 243-245
  
• Adrian Chirila-Rus, Kristof Denolf, Bart Vanhoof, Paul R. Schumacher, Kees A. Vissers:
  Communication Primitives Driven Hardware Design and Test Methodology Applied on Complex Video Applications. 246-249
  
• Thomas S. Hall, Kenneth B. Kent:
  Thread-Level Parallel Execution in Co-Designed Virtual Machines. 249-251
  

Hardware Prototyping

• Arnaldo Azevedo, Luciano Volcan Agostini, Flávio Rech Wagner, Sergio Bampi:
  Accelerating a Multiprocessor Reconfigurable Architecture with Pipelined VLIW Units. 255-257
  
• Rolf Drechsler, Görschwin Fey, Christian Genz, Daniel Große:
  SyCE: An Integrated Environment for System Design in SystemC. 258-260
  
• Nikolaos Kostaras, Haridimos T. Vergos:
  KoVer: A Sophisticated Residue Arithmetic Core Generator. 261-263
  
• Ami Castonguay, Yvon Savaria:
  A HyperTransport Chip-to-Chip Interconnect Tunnel Developed Using SystemC. 264-266
  
• S. W. Song, J. D. Zheng, William B. Gardner:
  Prototyping a Residential Gateway Using Xilinx ISE. 267-269
  

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