ReCoSoC 2005: Montpellier, France
Gilles Sassatelli, Manfred Glesner, Lionel Torres, Leandro Soares Indrusiak, Thomas Hollstein (Eds.): Proceedings of the 1st International Workshop on Reconfigurable Communication-centric Systems-on-Chip, ReCoSoC 2005, Montpellier, France, June 2005. Univ. Montpellier II 2005 ISBN 2-9517-4611-3- Yves Lhuillier, Pierre Palatin, Olivier Temam: Symbiotic Processing: Toward a Better Balance Between Architecture, Compiler and User Efforts. 9-18
- Christophe Gouyen, Loïc Lagadec, Bernard Pottier, A. André, E. Lepicier, François Dupont: Compiler level integration of a portable CAD framework for reconfigurable circuits. 19-26
- Frank Hannig, Hritam Dutta, Alexey Kupriyanov, Jürgen Teich, Rainer Schaffer, Sebastian Siegel, Renate Merker, Ronan Keryell, Bernard Pottier, Daniel Chillet, Daniel Menard, Olivier Sentieys: Co-Design of Massively Parallel Embedded Processor Architectures. 27-34
- Jürgen Becker, Michael Hübner, Katarina Paulsson, Alexander Thomas: Dynamic Reconfiguration On-Demand: Real-time Adaptivity in Next Generation Microelectronics. 35-42
- Peter Zipf, Claude Stötzler, Manfred Glesner: Analysis and Architectural Study of a Hybrid ASIC/Configurable State Machine Model. 53-58
- Hayder Mrabet, Zied Marrakchi, Habib Mehrez, André Tissot: Implementation of Scalable Embedded FPGA for SOC. 59-62
- Jean-Philippe Diguet, Yvan Eustache, Nader Ben Amor, Soufien Hammami: Feedback control modelling for learning reconfigurable embedded systems. 63-70
- François Verdier, Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Daniel Chillet, Sébastien Pillement: Exploring RTOS issues with a high-level model of a reconfigurable SoC platform. 71-78
- Leandro Soares Indrusiak, Manfred Glesner: Experiences on Actor-oriented Design of Reconfigurable Systems. 79-84
- Thomas Hollstein, Sujan Pandey, Manfred Glesner: Advanced On-Chip Communication Architectures and Routing Methods for Systems-on-Chip. 85-92
- Julien Delorme, Dominique Houzet, Romain Lemaire, Didier Lattard: Proposition of a benchmark for evaluation of cores mapping onto NoC architectures. 93-98
- Laurent Fesquet, Jerome Quartana, Marc Renaudin: Asynchronous Systems on Programmable Logic. 105-112
- Nicolas Bruchon, Gaston Cambon, Lionel Torres, Gilles Sassatelli: Non-volatile SRAM-FPGA based on magnetic tunnelling junction. 113-120
- Ian O'Connor, Matthieu Briere, Emmanuel Drouard, Art Kazmierczak, Faress Tissafi-Drissi, David Navarro, Fabien Mieyeville, Joni Dambre, Dirk Stroobandt, Jean-Marc Fedeli, Zbigniew Lisik, Frédéric Gaffiot: Towards reconfigurable optical networks on chip. 121-128
- Pierre Boulet, Arnaud Cuccuru, Jean-Luc Dekeyser, Ashish Meena: Model Driven Engineering for Regular MPSoC Co-design. 129-136
- Nathalie Julien, Johann Laurent, Eric Senn, David Elléouet, Yannig Savary, Nabil Abdelli, J. Ktari: Power/Energy Estimation in SoCs by Multi-Level Parametric Modeling. 137-142
- Luís Gomes, João Paulo Barros, Anikó Costa, Rui Pais, Filipe Moutinho: Formal methods for Embedded Systems Co-design: the FORDESIGN project. 143-150
- Tudor Murgan, Abdulfattah Mohammad Obeid, Andre Guntoro, Peter Zipf, Manfred Glesner, Ulrich Heinkel: Design and Implementation of a Multi-Core Architecture for Overhead Processing in Optical Transport Networks. 151-156
Posters
- Alfredo Rosado Muñoz, Emilio Soria-Olivas, Joan Vila-Francés, Jordi Muñoz-Marí, Javier Calpe-Maravilla: Implementation Challenges in Complex Adaptive Systems. 157-162
- Nicolas Valette, Lionel Torres, Frédéric Bancel, Nicolas Bérard: Integration of Reconfigurable Logic on Secure Circuits. 163-168
- Daniel Mesquita, Jean-Denis Techer, Lionel Torres, Gilles Sassatelli, Gaston Cambon, Michel Robert, Fernando Moraes: A new hardware countermeasure for masking power signatures of crypto cores. 169-176
- AbdelHalim Samahi, Sami Boukhechem, El-Bay Bourennane, Nasser E. Idirene: STARSoC : A C-based platform for rapid prototyping of embedded system. 177-182
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last updated on 2013-06-18T214307 by the dblp team