ReConFig 2008: Cancun, Quintana Roo, Mexico

General Session 1 - Applications 1

• Xuan Zhang, Cesar Ortega-Sanchez, Iain Murray:
  Reconfigurable PDA for the Visually Impaired Using FPGAs. 1-6
  
• Cesar Torres-Huitzil, Bernard Girau, Amine M. Boumaza, Bruno Scherrer:
  Embedded Harmonic Control for Trajectory Planning in Large Environments. 7-12
  
• Jose Hugo Barron-Zambrano, Cesar Torres-Huitzil, Mauricio Cerda:
  Flexible Architecture for Three Classes of Optical Flow Extraction Algorithms. 13-18
  

General Session 2 - Processors 1

• Harold Ishebabi, Philipp Mahr, Christophe Bobda:
  Automatic Synthesis of Multiprocessor Systems from Parallel Programs under Preemptive Scheduling. 19-24
  
• Xiaofang Wang, Swetha Thota:
  Design and Implementation of a Resource-Efficient Communication Architecture for Multiprocessors on FPGAs. 25-30
  
• Carlo Galuzzi, Dimitris Theodoropoulos, Roel Meeuws, Koen Bertels:
  Automatic Instruction-Set Extensions with the Linear Complexity Spiral Search. 31-36
  

General Session 3 - Applications 2

• Anders Kjær-Nielsen, Lars Baunegaard With Jensen, Anders Stengaard Sørensen, Norbert Krüger:
  A Real-Time Embedded System for Stereo Vision Preprocessing Using an FPGA. 37-42
  
• Anabel Morales-Cortes, Ramon Parra-Michel, Luis F. Gonzalez-Perez, Gabriela Cervantes T.:
  Finite Precision Analysis of the 3GPP Standard Turbo Decoder for Fixed-Point Implementation in FPGA Devices. 43-48
  
• Jose Hugo Barron-Zambrano, Fernando Martin del Campo-Ramirez, Miguel Arias-Estrada:
  Parallel Processor for 3D Recovery from Optical Flow. 49-54
  
• Song Sun, Michael Steffen, Joseph Zambreno:
  A Reconfigurable Platform for Frequent Pattern Mining. 55-60
  

General Session 4 - Reconfigurability

• Jean-Christophe Prévotet, Mohamed El Amine Benkhelifa, Bertrand Granado, Emmanuel Huck, Benoit Miramond, François Verdier, Daniel Chillet, Sébastien Pillement:
  A Framework for the Exploration of RTOS Dedicated to the Management of Hardware Reconfigurable Resources. 61-66
  
• Sven Eisenhardt, Tobias Oppold, Thomas Schweizer, Wolfgang Rosenstiel:
  Optimizing Partial Reconfiguration of Multi-context Architectures. 67-72
  
• Yi-Hua E. Yang, Viktor K. Prasanna:
  Automatic Construction of Large-Scale Regular Expression Matching Engines on FPGA. 73-78
  
• Juan Antonio Clemente, Carlos González, Javier Resano, Daniel Mozos:
  A Hardware Task-Graph Scheduler for Reconfigurable Multi-tasking Systems. 79-84
  

General Session 5 - Processors 2

• Gabriel Caffarena, Juan A. López, Gerardo Leyva, Carlos Carreras, Octavio Nieto-Taladriz:
  Optimized Architectural Synthesis of Fixed-Point Datapaths. 85-90
  
• Manuel Hernandez Calviño, Sergio Ruben Geninatti, Jose Ignacio Benavides Benitez:
  Developing an MMX Extension for the MicroBlaze Soft Processor. 91-96
  

General Session 6 - Methodologies 1

• Francesco Redaelli, Marco D. Santambrogio, Seda Ogrenci Memik:
  An ILP Formulation for the Task Graph Scheduling Problem Tailored to Bi-dimensional Reconfigurable Architectures. 97-102
  
• Rafael A. Arce-Nazario, Manuel Jiménez, Domingo Rodríguez:
  Architectural Model and Resource Estimation for Distributed Hardware Implementation of Discrete Signal Transforms. 103-108
  
• Alessio Montone, Francesco Redaelli, Marco D. Santambrogio, Seda Ogrenci Memik:
  A Reconfiguration-Aware Floorplacer for FPGAs. 109-114
  
• Umer Farooq, Zied Marrakchi, Hayder Mrabet, Habib Mehrez:
  The Effect of LUT and Cluster Size on a Tree Based FPGA Architecture. 115-120
  

General Session 7 - Methodologies 2

• Husain Parvez, Zied Marrakchi, Habib Mehrez:
  Enhanced Methodology and Tools for Exploring Domain-Specific Coarse-Grained FPGAs. 121-126
  
• Günter Knittel, Stefanie Mayer, Christian Rothländer:
  Integrating Logic Analyzer Functionality into VHDL Designs. 127-132
  
• Tom Degryse, Karel Bruneel, Harald Devos, Dirk Stroobandt:
  Loop Transformations to Reduce the Dynamic FPGA Recon?guration Overhead. 133-138
  
• Juan Galindo, Eric Peskin, Brad Larson, Gene Roylance:
  Leveraging Firmware in Multichip Systems to Maximize FPGA Resources: An Application of Self-Partial Reconfiguration. 139-144
  
• Rohit Saraswat, Brandon Eames:
  Finite Domain Constraints Based Delay Aware Placement Tool for FPOAs. 145-150
  

General Session 8 - Processors 3 and Applications 3

• David M. Cambre, Eduardo I. Boemo, Elias Todorovich:
  Arithmetic Operations and Their Energy Consumption in the Nios II Embedded Processor. 151-156
  
• Pablo Huerta, Javier Castillo, Carlos Sanchez, José Ignacio Martínez:
  Operating System for Symmetric Multiprocessors on FPGA. 157-162
  
• Luiza M. N. Coutinho, José Leandro D. Mendes, Carlos A. P. S. Martins:
  Dynamically Reconfigurable Split Cache Architecture. 163-168
  
• Armando Astarloa, Unai Bidarte, Jesús Lázaro, Jon Andreu, José Luis Martín:
  Configurable-System-on-Programmable-Chip for Power Electronics Control Applications. 169-174
  
• Nikolay Yu. Sorokin:
  Parallel Backprojector for Cone-Beam Computer Tomography. 175-180
  

General Session 9 - Systems on Chip

• Rachid Dafali, Jean-Philippe Diguet, M. Sevaux:
  Key Research Issues for Reconfigurable Network-on-Chip. 181-186
  
• Philipp Mahr, Christian Lorchner, Harold Ishebabi, Christophe Bobda:
  SoC-MPI: A Flexible Message Passing Library for Multiprocessor Systems-on-Chips. 187-192
  
• Zai Jian Jia, Tomás Bautista, Antonio Núñez, Cayetano Guerra, Mario Hernández:
  Design Space Exploration and Performance Analysis for the Modular Design of CVS in a Heterogeneous MPSoC. 193-198
  

General Session 10 - Reconfiguration and Methods

• Elmar Weber, Florian Dittmann, Norma Montealegre:
  Part-E - A Tool for Reconfigurable System Design. 199-204
  
• Christian A. Morillas, Juan Pedro Cobos, Francisco J. Pelayo, Alberto Prieto, Samuel F. Romero:
  VIS2SOUND on Reconfigurable Hardware. 205-210
  
• Yana Esteves Krasteva, Francisco Criado, Eduardo de la Torre, Teresa Riesgo:
  A Fast Emulation-Based NoC Prototyping Framework. 211-216
  
• Sohan Purohit, Sai Rahul Chalamalasetti, Martin Margala, Pasquale Corsonello:
  Power-Efficient High Throughput Reconfigurable Datapath Design for Portable Multimedia Devices. 217-222
  

Track on Bioinspired Reconfigurable Computing Systems and Self-Adaptive Computing 1

• Karel Bruneel, Dirk Stroobandt:
  Reconfigurability-Aware Structural Mapping for LUT-Based FPGAs. 223-228
  
• Bernard Girau, Cesar Torres-Huitzil:
  Fast Implementation of a Bio-inspired Model for Decentralized Gathering. 229-234
  
• Diego Puschini, Fabien Clermidy, Pascal Benoit, Gilles Sassatelli, Lionel Torres:
  Game-Theoretic Approach for Temperature-Aware Frequency Assignment with Task Synchronization on MP-SoC. 235-240
  

Track on Bioinspired Reconfigurable Computing Systems and Self-Adaptive Computing 2

• Lars Baunegaard With Jensen, Anders Kjær-Nielsen, Javier Diaz Alonso, Eduardo Ros, Norbert Krüger:
  A Hybrid FPGA/Coarse Parallel Processing Architecture for Multi-modal Visual Feature Descriptors. 241-246
  
• Yuken Kishimoto, Shinichiro Haruyama, Hideharu Amano:
  Design and Implementation of Adaptive Viterbi Decoder for Using A Dynamic Reconfigurable Processor. 247-252
  
• Alécio Pedro Delazari Binotto, Edison Pignaton de Freitas, Marcelo Götz, Carlos Eduardo Pereira, André Stork, Tony Larsson:
  Dynamic Self-Rescheduling of Tasks over a Heterogeneous Platform. 253-258
  

Track on High Performance Reconfigurable Computing 1

• Scott Lloyd, Quinn Snell:
  Sequence Alignment with Traceback on Reconfigurable Hardware. 259-264
  
• Manuel Saldaña, Emanuel Ramalho, Paul Chow:
  A Message-Passing Hardware/Software Co-simulation Environment to Aid in Reconfigurable Computing Design Using TMD-MPI. 265-270
  
• Simon Banks, Philip Beadling, Andras Ferencz:
  FPGA Implementation of Pseudo Random Number Generators for Monte Carlo Methods in Quantitative Finance. 271-276
  
• Juan A. Rico-Gallego, Jesús M. Álvarez Llorente, Francisco J. Perogil-Duque, Pedro P. Antunez-Gomez, Juan Carlos Díaz Martín:
  A Pthreads-Based MPI-1 Implementation for MMU-Less Machines. 277-282
  
• Ashwin A. Mendon, Ron Sass:
  A Hardware Filesystem Implementation for High-Speed Secondary Storage. 283-288
  

Track on High Performance Reconfigurable Computing 2

• Roque Alfredo Osornio-Rios, René de Jesús Romero-Troncoso, Luis Morales-Velazquez, J. Jesus de Santiago-Perez, Jesus Rooney Rivera-Guillen, Jose de Jesus Rangel-Magdaleno:
  A Real-Time FPGA Based Platform for Applications in Mechatronics. 289-294
  
• Humberto Calderon, Jesús Ortiz, Jean-Guy Fontaine:
  Disparity Map Hardware Accelerator. 295-300
  
• Abdulhadi Shoufan, Sorin A. Huss, Oliver Kelm, Sebastian Schipp:
  A Novel Rekeying Message Authentication Procedure Based on Winternitz OTS and Reconfigurable Hardware Architectures. 301-306
  
• Paulo Sérgio Brandão do Nascimento, Victor Wanderley Costa de Medeiros, Viviane Lucy Santos de Souza, Abner Correa Barros, Manoel Eusebio de Lima:
  A Temporal Partitioning Methodology for Reconfigurable High Performance Computers. 307-312
  
• Syed Zahid Ahmed, Julien Eydoux, Michael Fernández, Laurent Rouge, Gilles Sassatelli, Lionel Torres:
  Power Consumption Reduction Explorations in Processors by Enhancing Performance Using Small ESL Reprogrammable eFPGAs. 313-318
  

Track on Reconfigurable Computing for DSP and Communications 1

• Abdulrahman Hanoun, Friedrich Mayer-Lindenberg, Bassel Soudan:
  Reconfigurable Cell Architecture for Systolic and Pipelined Computing Datapaths. 319-324
  
• Bin Zhou, David Hwang:
  Implementations and Optimizations of Pipeline FFTs on Xilinx FPGAs. 325-330
  
• Suhaib A. Fahmy:
  Generalised Parallel Bilinear Interpolation Architecture for Vision Systems. 331-336
  

Track on Reconfigurable Computing for DSP and Communications 2

• C. Gonzalez-Concejero, Victoria Rodellar, Agustín Álvarez Marquina, Elvira Martínez de Icaya, Pedro Gómez Vilda:
  An FFT/IFFT Design versus Altera and Xilinx Cores. 337-342
  
• Zain-ul-Abdin, Bertil Svensson:
  Using a CSP Based Programming Model for Reconfigurable Processor Arrays. 343-348
  
• Sheng Cheng, Chien-Hsun Tseng, Marina Cole:
  A Novel FPGA Implementation of a Wideband Sonar System for Target Motion Estimation. 349-354
  
• Fernando Martin del Campo, René Cumplido, Roberto Perez-Andrade, Aldo G. Orozco-Lugo:
  Hybrid Architecture for Data-Dependent Superimposed Training in Digital Receivers. 355-360
  

Track on Reconfigurable Computing for DSP and Communications 3

• Ruzica Jevtic, Carlos Carreras, Domenik Helms:
  A Comparison of Approaches for High-Level Power Estimation of LUT-Based DSP Components. 361-366
  
• Jose Juan Garcia-Hernandez, Claudia Feregrino Uribe, René Cumplido:
  FPGA Implementation of a Modulated Complex Lapped Transform for Watermarking Systems. 367-372
  
• Christophe Desmouliers, Erdal Oruklu, Jafar Saniie:
  Universal Wavelet Kernel Implementation Using Reconfigurable Hardware. 373-378
  
• Carlos R. Sanchez-Ortiz, Ramon Parra-Michel, M. E. Guzman-Renteria:
  Design and Implementation of a Multi-standard Interleaver for 802.11a, 802.11n, 802.16e & DVB Standards. 379-384
  

Track on Reconfigurable Computing for Security and Cryptography 1

• Knut Wold, Chik How Tan:
  Analysis and Enhancement of Random Number Generator in FPGA Based on Oscillator Rings. 385-390
  
• Ersin Oksuzoglu, Erkay Savas:
  Parametric, Secure and Compact Implementation of RSA on FPGA. 391-396
  
• Ilker Yavuz, Siddika Berna Ors Yalcin, Çetin Kaya Koç:
  FPGA Implementation of an Elliptic Curve Cryptosystem over GF(3^m). 397-402
  

Track on Reconfigurable Computing for Security and Cryptography 2

• Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki:
  Enhanced Correlation Power Analysis Using Key Screening Technique. 403-408
  
• Övünç Kocabas, Erkay Savas, Johann Großschädl:
  Enhancing an Embedded Processor Core with a Cryptographic Unit for Speed and Security. 409-414
  
• Victor Lomné, Thomas Ordas, Philippe Maurine, Lionel Torres, Michel Robert, Rafael Soares, Ney Calazans:
  Triple Rail Logic Robustness against DPA. 415-420
  
• Ignacio Algredo-Badillo, Claudia Feregrino Uribe, René Cumplido, Miguel Morales-Sandoval:
  FPGA Implementation and Performance Evaluation of AES-CCM Cores for Wireless Networks. 421-426
  
• Mohamed El-Hadedy, Danilo Gligoroski, Svein J. Knapskog:
  High Performance Implementation of a Public Key Block Cipher - MQQ, for FPGA Platforms. 427-432
  
• Dimitrios Meintanis, Ioannis Papaefstathiou:
  Power Consumption Estimations vs Measurements for FPGA-Based Security Cores. 433-437
  

Track on Reconfigurable Computing for Security and Cryptography 3

• Daniele Fronte, Annie Pérez, Eric Payrat:
  Celator: A Multi-algorithm Cryptographic Co-processor. 438-443
  
• Z. Jezabel Guzman Zavaleta, Claudia Feregrino Uribe, René Cumplido:
  A Reversible Data Hiding Algorithm for Radiological Medical Images and Its Hardware Implementation. 444-449
  
• David Champagne, Reouven Elbaz, Catherine H. Gebotys, Lionel Torres, Ruby B. Lee:
  Forward-Secure Content Distribution to Reconfigurable Hardware. 450-455
  

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