21. PATMOS 2011: Madrid, Spain
José L. Ayala, Braulio García-Cámara, Manuel Prieto, Martino Ruggiero, Gilles Sicard (Eds.): Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation - 21st International Workshop, PATMOS 2011, Madrid, Spain, September 26-29, 2011. Proceedings. Springer 2011 Lecture Notes in Computer Science ISBN 978-3-642-24153-6- Mustafa Aktan, Dursun Baran, Vojin G. Oklobdzija: A Quick Method for Energy Optimized Gate Sizing of Digital Circuits. 1-10
- Ignacio Arnaldo, José L. Risco-Martín, José L. Ayala, José Ignacio Hidalgo: Power Profiling-Guided Floorplanner for Thermal Optimization in 3D Multiprocessor Architectures. 11-21
- Andrea Bartolini, MohammadSadegh Sadri, Francesco Beneventi, Matteo Cacciari, Andrea Tilli, Luca Benini: A System Level Approach to Multi-core Thermal Sensors Calibration. 22-31
- Abdullah Baz, Delong Shang, Fei Xia, Alexandre Yakovlev, Alexandre V. Bystrov: Improving the Robustness of Self-timed SRAM to Variable Vdds. 32-42
- José V. Busquets-Mataix, Carlos Catalá, Antonio Martí Campoy: Architecture Extensions for Efficient Management of Scratch-Pad Memory. 43-52
- Panagiotis Chaourani, Ilias Pappas, Spiros Nikolaidis, Abdoul Rjoub: Pass Transistor Operation Modeling for Nanoscale Technologies. 53-62
- Ning Chen, Bing Li, Ulf Schlichtmann: Iterative Timing Analysis Considering Interdependency of Setup and Hold Times. 73-82
- Gregory di Pendina, Kholdoun Torki, Guillaume Prenat, Yoann Guillemenet, Lionel Torres: Ultra Compact Non-volatile Flip-Flop for Low Power Digital Circuits Based on Hybrid CMOS/Magnetic Technology. 83-91
- Georgios D. Dimou, Peter A. Beerel, Andrew Lines: Performance-Driven Clustering of Asynchronous Circuits. 92-101
- Ahmed Yasir Dogan, David Atienza, Andreas Burg, Igor Loi, Luca Benini: Power/Performance Exploration of Single-core and Multi-core Processor Approaches for Biomedical Signal Processing. 102-111
- Thomas Ebi, Holm Rauchfuss, Andreas Herkersdorf, Jörg Henkel: Agent-Based Thermal Management Using Real-Time I/O Communication Relocation for 3D Many-Cores. 112-121
- Nicolas Ferry, Sylvain Ducloyer, Nathalie Julien, Dominique Jutel: Energy Estimator for Weather Forecasts Dynamic Power Management of Wireless Sensor Networks. 122-132
- Ignacio Herrera-Alzu, Marisa López-Vallejo: Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs. 133-142
- Henry X. F. Huang, Steven R. S. Shen, James B. Kuo: Cell-Based Leakage Power Reduction Priority (CBLPRP) Optimization Methodology for Designing SOC Applications Using MTCMOS Technique. 143-151
- Toshihiro Kameda, Hiroaki Konoura, Yukio Mitsuyama, Masanori Hashimoto, Takao Onoye: NBTI Mitigation by Giving Random Scan-in Vectors during Standby Mode. 152-161
- Hossein Karimiyan, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino: An On-Chip All-Digital PV-Monitoring Architecture for Digital IPs. 162-172
- Alireza Khosropour, Hossein Aghababa, Ali Afzali-Kusha, Behjat Forouzandeh: Chip Level Statistical Leakage Power Estimation Using Generalized Extreme Value Distribution. 173-179
- Mostafa Kishani, Amirali Baniasadi, Hossein Pedram: Using Silent Writes in Low-Power Traffic-Aware ECC. 180-192
- Christoph Knoth, Carsten Uphoff, Sebastian Kiesel, Ulf Schlichtmann: SWAT: Simulator for Waveform-Accurate Timing Including Parameter Variations and Transistor Aging. 193-203
- Lingamneni Avinash, Christian C. Enz, Krishna V. Palem, Christian Piguet: Parsimonious Circuits for Error-Tolerant Applications through Probabilistic Logic Minimization. 204-213
- Karthikeyan Lingasubramanian, Andrea Calimera, Alberto Macii, Enrico Macii, Massimo Poncino: Sub-Row Sleep Transistor Insertion for Concurrent Clock-Gating and Power-Gating. 214-225
- Ons Mbarek, Alain Pegatoquet, Michel Auguin: A Methodology for Power-Aware Transaction-Level Models of Systems-on-Chip Using UPF Standard Concepts. 226-236
- Takumi Okuhira, Tohru Ishihara: Unified Gated Flip-Flops for Reducing the Clocking Power in Register Circuits. 237-246
- Florent Ouchet, Katell Morin-Allory, Laurent Fesquet: C-elements for Hardened Self-timed Circuits. 247-256
- Abdelkrim Kamel Oudjida, Nicolas Chaillet, Ahmed Liacha, Mustapha Hamerlain, Mohamed Lamine Berrandjia: High-Speed and Low-Power PID Structures for Embedded Applications. 257-266
- Somayyeh Rahimian, Vasilis F. Pavlidis, Giovanni De Micheli: Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits. 267-277
- Amir-Mohammad Rahmani, Kameswar Rao Vaddina, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: Power and Area Optimization of 3D Networks-on-Chip Using Smart and Efficient Vertical Channels. 278-287
- Lars Schor, Hoeseok Yang, Iuliana Bacivarov, Lothar Thiele: Worst-Case Temperature Analysis for Different Resource Availabilities: A Case Study. 288-297
- Harry Sidiropoulos, Kostas Siozios, Dimitrios Soudris: A Framework for Architecture-Level Exploration of 3-D FPGA Platforms. 298-307
- Mariem Slimani, Fernando Silveira, Philippe Matherat: Variability-Speed-Consumption Trade-off in Near Threshold Operation. 308-316
- Rene van Leuken, Tom Van Leeuwen, Huib Lincklaen Arriens: High Level Synthesis of Asynchronous Circuits from Data Flow Graphs. 317-330
- Bruno Vaquie, Sébastien Tiran, Philippe Maurine: A Secure D Flip-Flop against Side Channel Attacks. 331-340
- Francesco Zanini, David Atienza, Giovanni De Micheli: Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling. 341-350
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last updated on 2013-06-18T214307 by the dblp team