5. NOCS 2011: Pittsburgh, Pennsylvania, USA

NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011. IEEE Computer Society 2011

Routing, Congestion Control and Deadlock Avoidance

José Cano, José Flich, José Duato, Marcello Coppola, Riccardo Locatelli:
Efficient routing implementation in complex systems-on-chip. 1-8
Nithin Michael, Milen Nikolov, Ao Tang, G. Edward Suh, Christopher Batten:
Analysis of application-aware on-chip routing under traffic uncertainty. 9-16
Najla Alfaraj, Junjie Zhang, Yang Xu, H. Jonathan Chao:
HOPE: Hotspot congestion control for Clos network on chip. 17-24
Freek Verbeek, Julien Schmaltz:
Automatic verification for deadlock in networks-on-chips with adaptive routing and wormhole switching. 25-32
Myong Hyon Cho, Keun Sup Shim, Mieszko Lis, Omer Khan, Srinivas Devadas:
Deadlock-free fine-grained thread migration. 33-40

Arpit Joshi, Madhu Mutyam:
Prevention flow-control for low latency torus networks-on-chip. 41-48
Hiroki Matsutani, Yasuhiro Take, Daisuke Sasaki, Masayuki Kimura, Yuki Ono, Yukinori Nishiyama, Michihiro Koibuchi, Tadahiro Kuroda, Hideharu Amano:
A vertical bubble flow network using inductive-coupling for 3-D CMPs. 49-56
Matt Grange, Roshan Weerasekera, Dinesh Pamunuwa, Axel Jantsch, Awet Yemane Weldezion:
Optimal network architectures for minimizing average distance in k-ary n-dimensional mesh networks. 57-64
Amir-Mohammad Rahmani, Pasi Liljeberg, Khalid Latif, Juha Plosila, Kameswar Rao Vaddina, Hannu Tenhunen:
Congestion aware, fault tolerant, and thermally efficient inter-layer communication scheme for hybrid NoC-bus 3D architectures. 65-72
Masoumeh Ebrahimi, Masoud Daneshtalab, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen:
Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model. 73-80

Yu-Hsiang Kao, H. Jonathan Chao:
BLOCON: A Bufferless Photonic Clos network-on-chip architecture. 81-88
Ahmed Abousamra, Rami G. Melhem, Alex K. Jones:
Two-hop Free-space based optical interconnects for chip multiprocessors. 89-96
Somayyeh Koohi, Meisam Abdollahi, Shaahin Hessabi:
All-optical wavelength-routed NoC based on a novel hierarchical topology. 97-104

Qiaoyan Yu, Meilin Zhang, Paul Ampadu:
Exploiting inherent information redundancy to manage transient errors in NoC routing arbitration. 105-112
Mohammad Reza Kakoee, Valeria Bertacco, Luca Benini:
A distributed and topology-agnostic approach for on-line NoC testing. 113-120
Cristinel Ababei, Hamed Sajjadi Kia, Om Prakash Yadav, Jingcao Hu:
Energy and reliability oriented mapping for regular Networks-on-Chip. 121-128
Onur Derin, Deniz Kabakci, Leandro Fiorin:
Online task remapping strategies for fault-tolerant Network-on-Chip multiprocessors. 129-136

Michael Papamichael, James C. Hoe, Onur Mutlu:
FIST: A fast, lightweight, FPGA-friendly packet latency estimator for NoC modeling in full-system simulations. 137-144
Danyao Wang, Natalie D. Enright Jerger, J. Gregory Steffan:
DART: A programmable architecture for NoC simulation on FPGAs. 145-152
Christopher Nitta, Kevin Macdonald, Matthew K. Farrens, Venkatesh Akella:
Inferring packet dependencies to improve trace based simulation of on-chip networks. 153-160
Yaniv Ben-Itzhak, Israel Cidon, Avinoam Kolodny:
Delay analysis of wormhole based heterogeneous NoC. 161-168

Amlan Ganguly, Paul Wettin, Kevin Chang, Partha Pratim Pande:
Complex network inspired fault-tolerant NoC architectures with wireless links. 169-176
Dan Zhao, Yi Wang, Jian Li, Takamaro Kikkawa:
Design of multi-channel wireless NoC to improve on-chip communication capacity! 177-184
Daniel Gebhardt, JunBok You, Kenneth S. Stevens:
Link pipelining strategies for an application-specific asynchronous NoC. 185-192
Gennette Gill, Sumedh S. Attarde, Geoffray Lacourba, Steven M. Nowick:
A low-latency adaptive asynchronous interconnection network using bi-modal router nodes. 193-200

Andreas Weichslgartner, Stefan Wildermann, Jürgen Teich:
Dynamic decentralized mapping of tree-structured applications on NoC architectures. 201-208
Zhonghai Lu:
Cross clock-domain TDM virtual circuits for networks on chips. 209-216
Giorgos Passas, Manolis Katevenis, Dionisios N. Pnevmatikatos:
VLSI micro-architectures for high-radix crossbar schedulers. 217-224
Tom English, Emanuel M. Popovici:
Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic accelerators. 225-232
Hyungjun Kim, Pritha Ghoshal, Boris Grot, Paul V. Gratz, Daniel A. Jimenez:
Reducing network-on-chip energy consumption through spatial locality speculation. 233-240

Amlan Ganguly, Partha Kundu, Pradip Bose:
Curbing energy cravings in networks: A cross-sectional view across the micro-macro boundary. 241-246
Christof Teuscher, Cristian Grecu, Ting Lu, Ron Weiss:
Challenges and promises of nano and bio communication networks. 247-254

James Hanlon:
The XMOS XK-XMP-64 development board. 255-256
Radu David, Paul Bogdan, Radu Marculescu, Ümit Y. Ogras:
Dynamic power management of voltage-frequency island partitioned Networks-on-Chip using Intel's Single-chip Cloud Computer. 257-258
Guopeng Wei, Paul Bogdan, Radu Marculescu:
A software framework for trace analysis targeting multicore platforms design. 259-260
Fabien Clermidy, N. Cassiau, N. Coste, Denis Dutoit, M. Fantini, Dimitri Ktenas, Romain Lemaire, L. Stefanizzi:
Reconfiguration of a 3GPP-LTE telecommunication application on a 22-core NoC-based system-on-chip. 261-262
Qiaoyan Yu, Meilin Zhang, Paul Ampadu:
A comprehensive Networks-on-Chip simulator for error control explorations. 263-264
Yaniv Ben-Itzhak, Eitan Zahavi, Israel Cidon, Avinoam Kolodny:
NoCs simulation framework for OMNeT++. 265-266
Florentine Dubois, José Cano, Marcello Coppola, José Flich, Frédéric Pétrot:
Spidergon STNoC design flow. 267-268

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