4. NOCS 2010: Grenoble, France
NOCS 2010, Fourth ACM/IEEE International Symposium on Networks-on-Chip, Grenoble, France, May 3-6, 2010. IEEE Computer Society 2010 ISBN 978-0-7695-4053-5
Keynote Abstracts
- Mohamad Sawan: Low-Power Bioelectronics for Massively Parallel Neuromonitoring. 3
- Keren Bergman: Photonic Chip-Scale Interconnection Networks for Performance-Energy Optimized Computing. 4
- Alessandro Cremonesi: Semiconductor Industry: Perspective, Evolution and Challenges. 5
Flow Control and Routing
- George Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis: Evaluating Bufferless Flow Control for On-chip Networks. 9-16
- Andreas Lankes, Thomas Wild, Andreas Herkersdorf, Sören Sonntag, Helmut Reinig: Comparison of Deadlock Recovery and Avoidance Mechanisms to Approach Message Dependent Deadlocks in On-chip Networks. 17-24
- Samuel Rodrigo, Jose Flich, Antoni Roca, Simone Medardoni, Davide Bertozzi, Jesus Camacho, Federico Silla, José Duato: Addressing Manufacturing Challenges with Cost-Efficient Fault Tolerant Routing. 25-32
GALS-Based NoC Design
- Carles Hernández, Antoni Roca, Federico Silla, Jose Flich, José Duato: Improving the Performance of GALS-Based NoCs in the Presence of Process Variation. 35-42
- Michael N. Horak, Steven M. Nowick, Matthew Carlberg, Uzi Vishkin: A Low-Overhead Asynchronous Interconnection Network for GALS Chip Multiprocessors. 43-50
- Tushar N. K. Jain, Paul V. Gratz, Alexander Sprintson, Gwan Choi: Asynchronous Bypass Channels: Improving Performance for Multi-synchronous NoCs. 51-58
Router Design
- Hiroki Matsutani, Michihiro Koibuchi, Daisuke Ikebuchi, Kimiyoshi Usami, Hiroshi Nakamura, Hideharu Amano: Ultra Fine-Grained Run-Time Power Gating of On-chip Routers for CMPs. 61-68
- Rohit Sunkam Ramanujam, Vassos Soteriou, Bill Lin, Li-Shiuan Peh: Design of a High-Throughput Distributed Shared-Buffer NoC Router. 69-78
- Young Hoon Kang, Taek-Jun Kwon, Jeffrey T. Draper: Fault-Tolerant Flow Control in On-chip Networks. 79-86
- Giorgos Passas, Manolis Katevenis, Dionisios N. Pnevmatikatos: A 128 x 128 x 24Gb/s Crossbar Interconnecting 128 Tiles in a Single Hop and Occupying 6% of Their Area. 87-95
Energy and Memory Efficiency
- Masoud Daneshtalab, Masoumeh Ebrahimi, Pasi Liljeberg, Juha Plosila, Hannu Tenhunen: A Low-Latency and Memory-Efficient On-chip Network. 99-106
- David Wolpert, Bo Fu, Paul Ampadu: Temperature-Aware Delay Borrowing for Energy-Efficient Low-Voltage Link Design. 107-114
- Daniel Gebhardt, JunBok You, Kenneth S. Stevens: Comparing Energy and Latency of Asynchronous and Synchronous NoCs for Embedded SoCs. 115-122
Application-Driven Optimization
- Nikita Nikitin, Satrajit Chatterjee, Jordi Cortadella, Michael Kishinevsky, Ümit Y. Ogras: Physical-Aware Link Allocation and Route Assignment for Chip Multiprocessing. 125-134
- Qiaoyan Yu, Paul Ampadu: Transient and Permanent Error Co-management Method for Reliable Networks-on-Chip. 145-154
- Jonas Diemer, Rolf Ernst: Back Suction: Service Guarantees for Latency-Sensitive On-chip Networks. 155-162
Topology and Architectures
- Francisco Gilabert Villamón, María Engracia Gómez, Simone Medardoni, Davide Bertozzi: Improved Utilization of NoC Channel Bandwidth by Switch Replication for Cost-Effective Multi-processor Systems-on-Chip. 165-172
- Chia-Hsin Owen Chen, Niket Agarwal, Tushar Krishna, Kyung-Hoae Koo, Li-Shiuan Peh, Krishna Saraswat: Physical vs. Virtual Express Topologies with Low-Swing Links for Future Many-Core NoCs. 173-180
- Yu-Hsiang Kao, Najla Alfaraj, Ming Yang, H. Jonathan Chao: Design of High-Radix Clos Network-on-Chip. 181-188
- Alexandre Guerre, Nicolas Ventroux, Raphaël David, Alain Mérigot: Hierarchical Network-on-Chip for Embedded Many-Core Architectures. 189-196
Emerging Technologies
- Randy Wayne Morris Jr., Avinash Karanth Kodi: Power-Efficient and High-Performance Multi-level Hybrid Nanophotonic Interconnect for Multicores. 207-214
- Paul Vincent Mejia, Rajeevan Amirtharajah, Matthew K. Farrens, Venkatesh Akella: Performance Evaluation of a Multicore System with Optically Connected Memory Modules. 215-222
- Chih-Hao Chao, Kai-Yuan Jheng, Hao-Yu Wang, Jia-Cheng Wu, An-Yeu Wu: Traffic- and Thermal-Aware Run-Time Thermal Management Scheme for 3D NoC Systems. 223-230
Traffic Modeling and Management
- Yvain Thonnart, Romain Lemaire, Fabien Clermidy: Distributed Sequencing for Resource Sharing in Multi-applicative Heterogeneous NoC Platforms. 233-240
- Paul Bogdan, Miray Kas, Radu Marculescu, Onur Mutlu: QuaLe: A Quantum-Leap Inspired Model for Non-stationary Analysis of NoC Traffic in Chip Multi-processors. 241-248
- Francesca Palumbo, Danilo Pani, Alessandro Pilia, Luigi Raffo: Impact of Half-Duplex and Full-Duplex DMA Implementations on NoC Performance. 249-256
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last updated on 2013-06-18T214307 by the dblp team