Architecture Verification

• 
  Vyas Venkataraman, Di Wang, Wei Qin, Mrinal Bose, Jayanta Bhadra: Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling. 3-8
• 
  Zdenek Prikryl, Karel Masarik, Tomas Hruska, Adam Husar: Fast Cycle-Accurate Interpreted Simulation. 9-14
• 
  Jack L. Mason: The importance of full target environment simulation tests for architecture validation. 15-18
• 
  Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha: A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations. 19-24

Mutation Analysis

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  Alper Sen: Mutation Operators for Concurrent SystemC Designs. 27-31
• 
  Nicola Bombieri, Franco Fummi, Graziano Pravadelli: On the Mutation Analysis of SystemC TLM-2.0 Standard. 32-37

Manufacturing Tests

• 
  József Sziray: Switch-Level Test Calculation for CMOS Circuits. 41-48
• 
  Jing Zeng, Jing Wang, Michael Mateja: A Path-Oriented Timing-Aware Diagnosis Methodology of At-Speed Transition Tests. 49-54
• 
  Shadi Moazzeni, Saadat Poormozaffari, Amin Emami: An Optimized Simulation-Based Fault Injection and Test Vector Generation Using VHDL to Calculate Fault Coverage. 55-60

Verification of Microprocessors and Complex IPs

• 
  Franco Fummi, Davide Quaglia, Sara Vinco, Giovanni Perbellini, Saul Saggin: Mixing Simulated and Actual Hardware Devices to Validate Device Drivers in a Complex Embedded Platform. 63-68
• 
  Chen-Yuan Kao, Chien-Hui Liao, Charles H.-P. Wen: An ILP-Based Diagnosis Framework for Multiple Open-Segment Defects. 69-72
• 
  Robert C. Page, Sakar Jain: Verification of the CoreNet Fabric with SystemVerilog. 73-78
• 
  Padmaraj Singh, David L. Landis, Vijaykrishnan Narayanan: Test Generation for Precise Interrupts on Out-of-Order Microprocessors. 79-82
• 
  Jim Holt, Jaideep Dastidar, David Lindberg, John Pape, Peng Yang: System-level Performance Verification of Multicore Systems-on-Chip. 83-87

Verification Methodologies

• 
  James A. Lear: Digital and Mixed-Signal Verification Differences. 91-94
• 
  Mona Safar, M. Watheq El-Kharashi, Mohamed Shalan, Ashraf Salem: A Reconfigurable Five-Stage Pipelined SAT Solver. 95-100
• 
  Daniel Große, Hoang M. Le, Rolf Drechsler: Induction-Based Formal Verification of SystemC TLM Designs. 101-106
• 
  Richard Bartolotti, Tom Burd, Brian McMinn, Arun Chandra: Constraint Management and Checking in Template-Based Circuit Designs. 107-113

last updated on Wed May 22 04:57:20 2013 by the dblp team
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