8. MTV 2009:
Austin,
TX,
USA
10th International Workshop on Microprocessor Test and Verification, MTV 2009, Austin, Texas, USA, 7-9 December 2009.
IEEE Computer Society 2009, ISBN 978-0-7695-4000-9
Architecture Verification
- Vyas Venkataraman, Di Wang, Wei Qin, Mrinal Bose, Jayanta Bhadra:
Simulation of a Heterogeneous System at Multiple Levels of Abstraction Using Rendezvous Based Modeling.
3-8
- Zdenek Prikryl, Karel Masarik, Tomas Hruska, Adam Husar:
Fast Cycle-Accurate Interpreted Simulation.
9-14
- Jack L. Mason:
The importance of full target environment simulation tests for architecture validation.
15-18
- Luis Angel D. Bathen, Yongjin Ahn, Nikil D. Dutt, Sudeep Pasricha:
A Methodology for Power-aware Pipelining via High-Level Performance Model Evaluations.
19-24
Mutation Analysis
Manufacturing Tests
Verification of Microprocessors and Complex IPs
- Franco Fummi, Davide Quaglia, Sara Vinco, Giovanni Perbellini, Saul Saggin:
Mixing Simulated and Actual Hardware Devices to Validate Device Drivers in a Complex Embedded Platform.
63-68
- Chen-Yuan Kao, Chien-Hui Liao, Charles H.-P. Wen:
An ILP-Based Diagnosis Framework for Multiple Open-Segment Defects.
69-72
- Robert C. Page, Sakar Jain:
Verification of the CoreNet Fabric with SystemVerilog.
73-78
- Padmaraj Singh, David L. Landis, Vijaykrishnan Narayanan:
Test Generation for Precise Interrupts on Out-of-Order Microprocessors.
79-82
- Jim Holt, Jaideep Dastidar, David Lindberg, John Pape, Peng Yang:
System-level Performance Verification of Multicore Systems-on-Chip.
83-87
Verification Methodologies
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