4. MTV 2003: Dallas, TX, USA

Fourth International Workshop on Microprocessor Test and Verification, Common Challenges and Solutions (MTV 2003), May 29-30, 2003, Hyatt Town Lake Hotel, Austin, Texas, USA. IEEE Computer Society 2003

@proceedings{DBLP:conf/mtv/2003,
  title     = {Fourth International Workshop on Microprocessor Test and Verification,
               Common Challenges and Solutions (MTV 2003), May 29-30, 2003,
               Hyatt Town Lake Hotel, Austin, Texas, USA},
  booktitle = {MTV},
  publisher = {IEEE Computer Society},
  year      = {2003},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

Functional Test Generation

Allon Adir, Roy Emek, Yoav Katz, Anatoly Koyfman:
DeepTrans - A Model-based Approach to Functional Verification of Address Translation Mechanisms. 3-6
Mrinal Bose, Mark H. Nodine, William R. Jurasz Jr., Vlad Zavadsky, Arvind Chodavadia, Lincoln R. Nunes:
Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification. 7-10
F. Hunsinger, Sebastien Francois, Ahmed Amine Jerraya:
Definition of a systematic method for the generation of software test programs allowing the functional verification of System On Chip (SoC). 11-

Special Session, Research at University of Texas and Texas A&M

Wangqi Qiu, D. M. H. Walker:
Testing the Path Delay Faults of ISCAS85 Circuit c6288. 19-

Issues in Microprocessor Test and Verification

V. V. Iyer:
Comparison of Verification Methodologies for Datapath Testing. 27-31
Jayanta Bhadra, Narayanan Krishnamurthy, Magdy S. Abadir:
A Methodology for Validating Manufacturing Test Vector Suites for Custom Designed Scan-Based Circuits. 32-37
Elham Safi, Zohreh Karimi, Maghsoud Abbaspour, Zainalabedin Navabi:
Utilizing Various ADL Facets for Instruction Level CPU Test. 38-

Debug and Diagnosis

Alexander Klaiber, Sinclair Chau:
Automatic Detection of Logic Bugs in Hardware Designs. 47-53
Yu-Shen Yang, Jiang Brandon Liu, Paul J. Thadikaran, Andreas G. Veneris:
Extraction Error Analysis, Diagnosis and Correction in Custom-Made High-Performance Designs. 54-59
Andreas G. Veneris:
Fault Diagnosis and Logic Debugging Using Boolean Satisfiability. 60-

SAT and ATPG

Ateet Bhalla, Inês Lynce, José T. de Sousa, João P. Marques Silva:
Heuristic Backtracking Algorithms for SAT. 69-74
Ohad Shacham, Emmanuel Zarpas:
Tuning the VSIDS Decision Heuristic for Bounded Model Checking. 75-

Embedded System Validation

Prabhat Mishra, Nikil D. Dutt:
A Methodology for Validation of Microprocessors using Equivalence Checking. 83-88
Alessandro Fin, Franco Fummi, Massimo Poncino, Graziano Pravadelli:
A SystemC-based Framework for Properties Incompleteness Evaluation. 89-94
Mahesh A. Iyer:
A Robust and Scalable Technique for the Constraints Solving Problem in High-Level Verification. 95-

Case Study

Joan Oliver, Octavian-Dumitru Mocanu, Carles Ferrer:
Energy Awareness through Software Optimisation as a Performance Estimate Case Study of the MC68HC908GP32 Microcontroller. 111-

High-Level Verification

Matthew W. Heath, Ian G. Harris:
A Deterministic Globally Asynchronous Locally Synchronousy Microprocessor Architecture. 119-

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