31. MICRO 1998: Dallas, Texas, USA

• Scott Rixner, William J. Dally, Ujval J. Kapasi, Brucek Khailany, Abelardo López-Lagunas, Peter R. Mattson, John D. Owens:
  A Bandwidth-efficient Architecture for Media Processing. 3-13
  
• Chia-Lin Yang, Barton Sano, Alvin R. Lebeck:
  Exploiting Instruction Level Parallelism in Geometry Processing for Three Dimensional Graphics Applications. 14-24
  
• Corinna G. Lee, Mark G. Stoodley:
  Simple Vector Microprocessors for Multimedia Applications. 25-36
  
• Ravi Bhargava, Lizy Kurian John, Brian L. Evans, Ramesh Radhakrishnan:
  Evaluating MMX Technology Using DSP and Multimedia Applications. 37-46
  
• Sangwook P. Kim, Gary S. Tyson:
  Analyzing the Working Set Characteristics of Branch Execution. 49-58
  
• Alexandre Farcy, Olivier Temam, Roger Espasa, Toni Juan:
  Dataflow Analysis of Branch Mispredictions and Its Application to Early Resolution of Branch Outcomes. 59-68
  
• A. N. Eden, Trevor N. Mudge:
  The YAGS Branch Prediction Scheme. 69-77
  
• T. N. Vijaykumar, Gurindar S. Sohi:
  Task Selection for a Multiscalar Processor. 81-92
  
• SangMin Shim, Soo-Mook Moon:
  Split-path Enhanced Pipeline Scheduling for Loops with Control Flows. 93-102
  
• Erik Nystrom, Alexandre E. Eichenberger:
  Effective Cluster Assignment for Modulo Scheduling. 103-114
  
• Cliff Young, Michael D. Smith:
  Better Global Scheduling Using Path Profiles. 115-123
  
• Glenn Reinman, Brad Calder:
  Predictive Techniques for Aggressive Load Speculation. 127-137
  
• Ben-Chung Cheng, Daniel A. Connors, Wen-mei W. Hwu:
  Compiler-Directed Early Load-Address Generation. 138-147
  
• Srikanth T. Srinivasan, Alvin R. Lebeck:
  Load Latency Tolerance in Dynamically Scheduled Processors. 148-159
  
• Lambert Schaelicke, Al Davis:
  Improving I/O Performance with a Conditional Store Buffer. 160-169
  
• Daniel H. Friendly, Sanjay J. Patel, Yale N. Patt:
  Putting the Fill Unit to Work: Dynamic Optimizations for Trace Cache Microprocessors. 173-181
  
• Chi-Keung Luk, Todd C. Mowry:
  Cooperative Prefetching: Compiler and Hardware Support for Effective Instruction Prefetching in Modern Processors. 182-194
  
• Guido Araujo, Paulo Centoducatte, Mario Cartes, Ricardo Pannain:
  Code Compression Based on Operand Factorization. 194-201
  
• Avinash Sodani, Gurindar S. Sohi:
  Understanding the Differences Between Value Prediction and Instruction Reuse. 205-215
  
• Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz:
  A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. 216-225
  
• Haitham Akkary, Michael A. Driscoll:
  A Dynamic Multithreading Processor. 226-236
  
• David López, Josep Llosa, Mateo Valero, Eduard Ayguadé:
  Widening Resources: A Cost-effective Technique for Aggressive ILP Architectures. 237-246
  
• Karel Driesen, Urs Hölzle:
  The Cascaded Predictor: Economical and Adaptive Branch Target Prediction. 249-258
  
• Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark:
  Improving Prediction for Procedure Returns with Return-address-stack Repair Mechanisms. 259-271
  
• John Kalamatianos, David R. Kaeli:
  Predicting Indirect Branches via Data Compression. 272-281
  
• Mahmut T. Kandemir, Alok N. Choudhary, J. Ramanujam, Prithviraj Banerjee:
  Improving Locality Using Loop and Data Transformations in an Integrated Framework. 285-297
  
• Timothy Kong, Kent D. Wilken:
  Precise Register Allocation for Irregular Architectures. 297-307
  
• Emre Özer, Sanjeev Banerjia, Thomas M. Conte:
  Unified Assign and Schedule: A New Approach to Scheduling for Clustered Register File Microarchitectures. 308-315
  

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