Google
Google Scholar
MS Academic
CiteSeerX
CORE
Semantic Scholar24. MICRO 1991: Albuquerque, New Mexico, USA
BibTeX
RIS
RDF N-Triples
XML
Twitter
Reddit
Mendeley
BibSonomy
LinkedIn
Google+
FacebookYashwant K. Malaiya:
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 24, Albuquerque, New Mexico, USA, November 18-20, 1991. ACM/IEEE 1991, ISBN 0-89791-460-0
Proceedings of the 24th Annual IEEE/ACM International Symposium on Microarchitecture, MICRO 24, Albuquerque, New Mexico, USA, November 18-20, 1991. ACM/IEEE 1991, ISBN 0-89791-460-0
Michael A. Schuette, John Paul Shen:
An Instruction-Level Performance Analysis of the Multiflow TRACE 14/300. 2-11
An Instruction-Level Performance Analysis of the Multiflow TRACE 14/300. 2-11
William Marcus Miller, Walid A. Najjar, A. P. Wim Böhm:
A Quantitative Analysis of Locality in Dataflow Programs. 12-18
A Quantitative Analysis of Locality in Dataflow Programs. 12-18
Jeffrey C. Becker, Arvin Park, Matthew K. Farrens:
An Analysis of the Information Content of Address Reference Streams. 19-24
An Analysis of the Information Content of Address Reference Streams. 19-24
Pohua P. Chang, William Y. Chen, Scott A. Mahlke, Wen-mei W. Hwu:
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors. 25-33
Comparing Static and Dynamic Code Scheduling for Multiple-Instruction-Issue Processors. 25-33
Michael Butler, Yale N. Patt:
The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling. 34-41
The Effect of Real Data Cache Behavior on the Performance of a Microarchitecture that Supports Dynamic Scheduling. 34-41
Matthew K. Farrens, Arvin Park:
Workload and Implementation Considerations for Dynamic Base Register Caching. 62-68
Workload and Implementation Considerations for Dynamic Base Register Caching. 62-68
William Y. Chen, Scott A. Mahlke, Pohua P. Chang, Wen-mei W. Hwu:
Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching. 69-73
Data Access Microarchitectures for Superscalar Processors with Compiler-Assisted Data Prefetching. 69-73
Jan Hoogerbrugge, Henk Corporaal, Hans Mulder:
Software Pipelining for Transport-Triggered Architectures. 74-81
Software Pipelining for Transport-Triggered Architectures. 74-81
Mark Smotherman, Sanjay Krishnamurthy, P. S. Aravind, David Hunnicutt:
Efficient DAG Construction and Heuristic Calculation for Instruction Scheduling. 93-102
Efficient DAG Construction and Heuristic Calculation for Instruction Scheduling. 93-102
David Bernstein, Doron Cohen, Hugo Krawczyk:
Code Duplication: An Assist for Global Instruction Scheduling. 103-113
Code Duplication: An Assist for Global Instruction Scheduling. 103-113
Mauricio Breternitz Jr., John Paul Shen:
Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors. 114-123
Implementation Optimization Techniques for Architecture Synthesis of Application-Specific Processors. 114-123
Robert A. Walker, Shivkumar Ramabadran, Rajive Joshi, Steinar Flatland:
Increasing User Interaction During High-Level Synthesis. 133-142
Increasing User Interaction During High-Level Synthesis. 133-142
Bruce K. Holmer, Alvin M. Despain:
Viewing Instruction Set Design as an Optimization Problem. 153-162
Viewing Instruction Set Design as an Optimization Problem. 153-162
Haigeng Wang, Alexandru Nicolau, Roni Potasman:
A New Technique for Induction Variable Removal. 172-180
A New Technique for Induction Variable Removal. 172-180
Gerben Essink, Emile H. L. Aarts, R. van Dongen, Piet J. van Gerwen, Jan H. M. Korst, Kees A. Vissers:
Architecture and Programming of a VLIW Style Programmable Video Signal Processor. 181-188
Architecture and Programming of a VLIW Style Programmable Video Signal Processor. 181-188
Samarina Makhdoom, Daniel Tabak, Richard Auletta:
Register/File/Cache Microarchitecture Study Using VHDL. 217-222
Register/File/Cache Microarchitecture Study Using VHDL. 217-222
maintained by 
at 
at 
data released under the ODC-BY 1.0 license; see also our legal information page
last updated on 2017-08-18 00:08 CEST by the dblp team