47. MICRO 2014: Cambridge, United Kingdom

Session 1A: Stacked DRAM

Session 1B: GPGPU and Data Parallel Architectures

Session 2A: Memory Systems, Scheduling, and Optimization

Session 2B: Security

Session 3A: Methodology, Modeling, and Tools

Session 3B: Reliability and Fault Tolerance

Session 4A: TLB and Cache Optimization

Session 4B: Managing Voltage and Time

Session 5A: Energy-Efficient Computation

Session 5B: Interconnects

Session 6A: Branch Prediction and Prefetching

Session 6B: Compilation and Code Generation

Session 7: Best Paper Nominees

maintained by Schloss Dagstuhl LZI at University of Trier