32. MICRO 1999: Haifa, Israel

Welcome and Keynote

• Fred J. Pollack:
  New Microarchitecture Challenges in the Coming Generations of CMOS Process Technologies. 2-
  

Faster FrontEnd

• Eric Rotenberg, James E. Smith:
  Control Independence in Trace Processors. 4-15
  
• Glenn Reinman, Brad Calder, Todd M. Austin:
  Fetch Directed Instruction Prefetching. 16-27
  
• Timothy H. Heil, Zak Smith, James E. Smith:
  Improving Branch Predictors by Correlating on Data Values. 28-37
  
• Artur Klauser, Dirk Grunwald:
  Instruction Fetch Mechanisms for Multipath Execution Processors. 38-
  

3D and MultiMedia

• Andrew Wolfe, Derek B. Noonburg:
  A Superscalar 3D Graphics Engine. 50-61
  
• Tulika Mitra, Tzi-cker Chiueh:
  Dynamic 3D Graphics Workload Characterization and the Architectural Implications. 62-71
  
• Jesús Corbal, Roger Espasa, Mateo Valero:
  Exploiting a New Level of DLP in Multimedia Applications. 72-
  

Efficient Embedded Processors

• Sergei Y. Larin, Thomas M. Conte:
  Compiler-Driven Cached Code Compression Schemes for Embedded ILP Processors. 82-92
  
• Charles Lefurgy, Eva Piccininni, Trevor N. Mudge:
  Evaluation of a High Performance Code Compression Method. 93-102
  
• Lea Hwang Lee, Jeff Scott, Bill Moyer, John Arends:
  Low-Cost Branch Folding for Embedded Applications with Small Tight Loops. 103-
  

Memory Hierarchy

• Santosh G. Abraham, Scott A. Mahlke:
  Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems. 114-125
  
• Jamison D. Collins, Dean M. Tullsen:
  Hardware Identification of Cache Conflict Misses. 126-135
  
• Sangyeun Cho, Pen-Chung Yew, Gyungho Lee:
  Access Region Locality for High-Bandwidth Processor Memory System Design. 136-146
  
• Vijay S. Pai, Sarita V. Adve:
  Code Transformations to Improve Memory Parallelism. 147-
  

Better Scheduling

• Daniel A. Connors, Wen-mei W. Hwu:
  Compiler-Directed Dynamic Computation Reuse: Rationale and Initial Results. 158-169
  
• Soner Önder, Rajiv Gupta:
  Dynamic Memory Disambiguation in the Presence of Out-of-Order Store Issuing. 170-176
  
• Andreas Moshovos, Gurindar S. Sohi:
  Read-After-Read Memory Dependence Prediction. 177-185
  
• Teresa Monreal, Antonio González, Mateo Valero, José González, Víctor Viñals:
  Delaying Physical Register Allocation through Virtual-Physical Registers. 186-
  

Invited Speaker

• Bruce Shriver:
  Core Technologies in Hardware and Software. 194-
  

Novel Microarchitectures and Multithreading

• Todd M. Austin:
  DIVA: A Reliable Substrate for Deep Submicron Microarchitecture Design. 196-207
  
• Mark Oskin, Justin Hensley, Diana Keen, Frederic T. Chong, Matthew K. Farrens, Aneet Chopra:
  Exploiting ILP in Page-based Intelligent Memory. 208-218
  
• Craig B. Zilles, Joel S. Emer, Gurindar S. Sohi:
  The Use of Multithreading for Exception Handling. 219-229
  
• Pedro Marcuello, Jordi Tubella, Antonio González:
  Value Prediction for Speculative Multithreaded Architectures. 230-
  

Low Power Enhancements

• Enric Musoll:
  Predicting the Usefulness of a Block Result: A Micro-Architectural Technique for High-Performance Low-Power Processors. 238-247
  
• David H. Albonesi:
  Selective Cache Ways: On-Demand Cache Resource Allocation. 248-
  

Compilers

• Jay Bharadwaj, Kishore N. Menezes, Chris McKinsey:
  Wavefront Scheduling: Path based Data Representation and Scheduling of Subgraphs. 262-271
  
• Alexandre E. Eichenberger, Waleed Meleis:
  Balance Scheduling: Weighting Branch Tradeoffs in Superblocks. 272-283
  
• Kemal Ebcioglu, Erik R. Altman, Sumedh W. Sathaye, Michael Gschwind:
  Optimizations and Oracle Parallelism with Dynamic Translation. 284-
  

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