27. MICRO 1994: San Jose, California, USA

@proceedings{DBLP:conf/micro/1994,
  title     = {Proceedings of the 27th Annual International Symposium on Microarchitecture,
               San Jose, California, USA, November 30 - December 2, 1994},
  booktitle = {MICRO},
  publisher = {ACM/IEEE},
  year      = {1994},
  isbn      = {0-89791-707-3},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

• Youfeng Wu, James R. Larus:
  Static branch frequency and program profile analysis. 1-11
  
• Thomas M. Conte, Burzin A. Patel, J. Stan Cox:
  Using branch handling hardware to support profile-driven optimization. 12-21
  
• Po-Yung Chang, Eric Hao, Tse-Yu Yeh, Yale N. Patt:
  Branch classification: a new mechanism for improving branch predictor performance. 22-31
  
• Andrew R. Pleszkun:
  Techniques for compressing program address traces. 32-39
  
• Michael S. Schlansker, Vinod Kathail, Sadun Anik:
  Height reduction of control recurrences for ILP processors. 40-51
  
• Derek B. Noonburg, John Paul Shen:
  Theoretical modeling of superscalar processor performance. 52-62
  
• B. Ramakrishna Rau:
  Iterative modulo scheduling: an algorithm for software pipelining loops. 63-74
  
• Alexandre E. Eichenberger, Edward S. Davidson, Santosh G. Abraham:
  Minimum register requirements for a modulo schedule. 75-84
  
• Ramaswamy Govindarajan, Erik R. Altman, Guang R. Gao:
  Minimizing register requirements under resource-constrained rate-optimal software pipelining. 85-94
  
• Jian Wang, Andreas Krall, M. Anton Ertl, Christine Eisenbeis:
  Software pipelining with register allocation and spilling. 95-99
  
• Peter Dahl, Matthew T. O'Keefe:
  Reducing memory traffic with CRegs. 100-104
  
• David Bernstein, Doron Cohen, Dror E. Maydan:
  Dynamic memory disambiguation for array references. 105-111
  
• Bogong Su, Stanley Habib, Wei Zhao, Jian Wang, Youfeng Wu:
  A study of pointer aliasing for software pipelining using run-time disambiguation. 112-117
  
• Yoji Yamada, John Gyllenhall, Grant E. Haab, Wen-mei W. Hwu:
  Data relocation and prefetching for programs with large data sets. 118-127
  
• Lishing Liu:
  Cache designs with partial address matching. 128-136
  
• Ching-Long Su, Alvin M. Despain:
  Minimizing branch misprediction penalties for superpipelined processors. 138-142
  
• Eric Sprangle, Yale N. Patt:
  Facilitating superscalar processing via a combined static/dynamic register renaming scheme. 143-147
  
• Raymond Lo, Sun Chan, Fred C. Chow, Shin-Ming Liu:
  Improving resource utilization of the MIPS R8000 via post-scheduling global instruction distribution. 148-152
  
• Michael Golden, Trevor N. Mudge:
  A comparison of two pipeline organizations. 153-161
  
• Manoj Franklin, Mark Smotherman:
  A fill-unit approach to multiple instruction issue. 162-171
  
• Rahul Razdan, Michael D. Smith:
  A high-performance microarchitecture with hardware-programmable functional units. 172-180
  
• Scott E. Breach, T. N. Vijaykumar, Gurindar S. Sohi:
  The anatomy of the register file in a multiscalar processor. 181-190
  
• Jan Hoogerbrugge, Henk Corporaal:
  Register file port requirements of transport triggered architectures. 191-195
  
• Gary S. Tyson:
  The effects of predicated execution on branch prediction. 196-206
  
• Jonathan P. Vogel, Bruce K. Holmer:
  Analysis of the conditional skip instructions of the HP precision architecture. 207-216
  
• Scott A. Mahlke, Richard E. Hank, Roger A. Bringmann, John C. Gyllenhaal, David M. Gallagher, Wen-mei W. Hwu:
  Characterizing the impact of predicated execution on branch prediction. 217-227
  
• Eric Hao, Po-Yung Chang, Yale N. Patt:
  The effect of speculatively updating branch history on branch prediction accuracy, revisited. 228-232
  

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