22. MICRO 1989: Dublin, Ireland

@proceedings{DBLP:conf/micro/1989,
  title     = {Proceedings of the 22nd Annual Workshop and Symposium on Microprogramming
               and Microarchitecture, 1989, Dublin, Ireland, August 14-16, 1989},
  booktitle = {MICRO},
  publisher = {ACM/IEEE},
  year      = {1989},
  bibsource = {DBLP, http://dblp.uni-trier.de}
}

• K. Lall, J. William Atwood:
  A microprogrammed interpreter for concurrent Euclid. 1-10
  
• Stephen J. Allan:
  Functional languages in microcode compilers. 11-20
  
• Fadi N. Sibai, L. Watson, M. Lu:
  Design and performance measurements of a parallel machine for the unification algorithm. 21-30
  
• M. Brady:
  A direct execution architecture for Prolog? 31-34
  
• Hans Mulder, R. J. Portier:
  Cost-effective design of application specific VLIW processors using the SCARCE framework. 35-42
  
• Toshio Nakatani, Kemal Ebcioglu:
  "Combining" as a compilation technique for VLIW architectures. 43-55
  
• Patrick M. Lenders, Heiko Schröder, Peter E. Strazdins:
  Microprogramming instruction systolic arrays. 56-69
  
• Rubin A. Parekhji, N. K. Nanda:
  Design methodology and microdiagnostics development for a self-checking microprocessor. 70-82
  
• L. A. Kovacs, S. F. Gilli:
  Extended microcode error checking on a pipelined machine. 83-87
  
• Yashwant K. Malaiya:
  On inherent untestability of unaugmented microprogrammed control. 88-96
  
• Giacomo R. Sechi:
  Abstract computing machines. 97-111
  
• Vicki H. Allan:
  Peephole optimization as a targeting and coupling tool. 112-121
  
• R. Katti, L. Manwaring:
  Information structures in language directed architectures. 122-126
  
• A. J. van de Goor, Henk Corporaal:
  DOAS: an object oriented architecture supporting secure languages. 127-134
  
• D. Liu, Wolfgang K. Giloi:
  A loop optimization technique based on scheduling table. 135-140
  
• Franco Gasperoni, Uwe Schwiegelshohn, Kemal Ebcioglu:
  On optimal loop parallelization. 141-147
  
• E. Sanchez:
  A microprogramming teaching environment using the Macintosh computer. 148-155
  
• A. Parker, James O. Hamblen:
  A VLSI based microprogramming evaluation system to support an instructional laboratory. 156-159
  
• Sergio D'Angelo, Giacomo R. Sechi:
  Definition of elementary arithmetic operations by using ACM. 160-162
  
• Pantung Wijaya, Vicki H. Allan:
  Incremental foresighted local compaction. 163-171
  
• J. L. Linn, C. D. Ardoin:
  All example of using pseudofields to eliminate version shuffling in horizontal code compaction. 172-180
  
• M. C. Ertem:
  Multiple operation memory structures. 181-187
  
• P.-H. Chang, Wen-mei W. Hwu:
  Forward semantic: a compiler-assisted instruction fetch method for heavily pipelined processors. 188-198
  
• Jong-Jiann Shieh, Christos A. Papachristou:
  On reordering instruction streams for pipelined computers. 199-206
  
• Colin C. Charlton, D. Jackson, Paul H. Leng:
  A functional model of clocked microarchitectures. 207-212
  
• Yale N. Patt:
  Microarchitecture choices (implementation of the VAX). 213-216
  
• John A. Nestor, Bassel Soudan, Zubair Mayet:
  MIES: a microarchitecture design tool. 217-222
  
• Hans Mulder, P. Stravers:
  A flexible VLSI core for an adaptable architecture. 223-231
  
• Edil S. Tavares Fernandes:
  A model for microarchitecture structure evaluation. 232-236
  
• Michael J. Flynn, R. I. Winner:
  ASIC microprocessors. 237-243
  
• Monica Alderighi, Giacomo R. Sechi, Roberto Vaccaro, Lorenzo Verdoscia:
  A computing unit for FFP function evaluation in support of correctness proofs. 244-253
  

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