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Semantic Scholar7. MEMOCODE 2009: Cambridge, Massachusetts, USA
7th ACM/IEEE International Conference on Formal Methods and Models for Codesign (MEMOCODE 2009), July 13-15, 2009, Cambridge, Massachusetts, USA. IEEE 2009, ISBN 978-1-4244-4806-7- Malay K. Ganai, Weihong Li:
Bang for the buck: Improvising and scheduling verification engines for effective resource utilization. 8-17 - Jeong-Han Yun, Chul-Joo Kim, Sunae Seo, Taisook Han, Kwang-Moo Choe:
Refining schizophrenia via graph reachability in Esterel. 18-27 - Luigi Di Guglielmo, Franco Fummi, Graziano Pravadelli:
The role of mutation analysis for property qualification. 28-35 - Hubert Garavel, Claude Helmstetter, Olivier Ponsini, Wendelin Serwe:
Verification of an industrial SystemC/TLM model using LOTOS and CADP. 46-55 - O. Sarbishei, Mahmoud Tabandeh, Bijan Alizadeh, Masahiro Fujita:
High-level optimization of integer multipliers over a finite bit-width with verification capabilities. 56-65 - Abhinav Agarwal, Nirav Dave, Kermin Fleming, Asif Khan, Myron King, Man Cheuk Ng, Muralidaran Vijayaraghavan:
Implementing a fast cartesian-polar matrix interpolator. 73-76 - Anita Lungu, Pradip Bose, Daniel J. Sorin, Steven German, Geert Janssen:
Multicore power management: Ensuring robustness via early-stage formal verification. 78-87 - Daniel W. Williams, Aprotim Sanyal, Dan Upton, Jason Mars, Sudeep Ghosh, Kim M. Hazelwood:
A cross-layer approach to heterogeneity and reliability. 88-97 - Eric S. Chung, James C. Hoe:
Implementing a high-performance multithreaded microprocessor: A case study in high-level design and validation. 98-107 - Marco Bozzano, Alessandro Cimatti, Marco Roveri, Joost-Pieter Katoen, Viet Yen Nguyen, Thomas Noll:
Codesign of dependable systems: A component-based modeling language. 121-130 - Fabrizio Ferrandi, Marco Lattuada, Christian Pilato, Antonino Tumeo:
Performance estimation for task graphs combining sequential path profiling and control dependence regions. 131-140 - Xavier Briand, Bertrand Jeannet:
Combining control and data abstraction in the verification of hybrid systems. 141-150 - Muralidaran Vijayaraghavan, Arvind:
Bounded Dataflow Networks and Latency-Insensitive circuits. 171-180
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last updated on 2017-07-23 22:30 CEST by the dblp team