4. MEMOCODE 2006: Napa, California, USA

Keynote Talk I

• Rajeev Alur:
  Games for formal design and verification of reactive systems. 3
  

Session I: Model Checking

• Tevfik Bultan, Constance L. Heitmeyer:
  Analyzing tabular requirements specifications using infinite state model checking. 7-16
  
• Zijiang Yang, Chao Wang, Aarti Gupta, Franjo Ivancic:
  Mixed symbolic representations for model checking software programs. 17-26
  
• Fei Xie, Guowu Yang, Xiaoyu Song:
  Component-based hardware/software co-verification. 27-36
  

Session II: Rule-based HW Design

• Hiren D. Patel, Sandeep K. Shukla, E. Mednick, Rishiyur S. Nikhil:
  A rule-based model of computation for SystemC: integrating SystemC and Bluespec for co-design. 39-48
  
• Gaurav Singh, Sandeep K. Shukla:
  Low-power hardware synthesis from TRS-based specifications. 49-58
  
• Nirav Dave, Michael Pellauer, S. Gerding, Arvind:
  802.11a transmitter: a case study in microarchitectural exploration. 59-68
  

Session III: HW Verification

• Shobha Vasudevan, Jacob A. Abraham, Vinod Viswanath, Jiajin Tu:
  Automatic decomposition for sequential equivalence checking of system level and RTL descriptions. 71-80
  
• Alistair A. McEwan, Steve Schneider:
  A verified development of hardware using CSP/spl par/B. 81
  

Panel I: Nano-Computing: Do we need New Formal Approaches to Co-Design?

• M. Hsiao, S. Shukla, M. Gokhale, Alvin R. Lebeck:
  Panel: Nano-computing - do we need new formal approaches? 85-86
  

Keynote Talk II

• Alexander Aiken:
  Scalable program analysis using Boolean satisfiability. 89
  

Session IV: Transaction-level Modeling

• Wolfgang Ecker, Volkan Esen, Michael Hull:
  Execution semantics and formalisms for multi-abstraction TLM assertions. 93-102
  
• Nicola Bombieri, Franco Fummi, Graziano Pravadelli:
  A methodology for abstracting RTL designs into TL descriptions. 103-112
  
• Niloofar Razavi, Marjan Sirjani:
  Using Reo for formal specification and verification of system designs. 113-122
  

Panel II: Programming Models and Languages for SOC-Implemented Architectures

• R. Gupta:
  Programming models and languages for SoC-implemented architectures. 125
  

Session V: Time and Clocks

• Myla Archer, Hongping Lim, Nancy A. Lynch, Sayan Mitra, Shinya Umeno:
  Specifying and proving properties of timed I/O automata in the TIOA toolkit. 129-138
  
• E. Czeck, Ravi Nanavati, Joseph E. Stoy:
  Reliable design with multiple clock domains. 139-148
  
• Flavius Gruian, Partha S. Roop, Zoran A. Salcic, Ivan Radojevic:
  The SystemJ approach to system-level design. 149-158
  

Keynote Talk III

• C. Seger:
  Integrating design and verification - from simple idea to practical system. 161
  

Session VI: Scheduling and Analysis

• Klaus Schneider, Jens Brandt, Eric Vecchié:
  Efficient code generation from synchronous programs. 165-174
  
• Julien Boucaron, Robert de Simone, Jean-Vivien Millo:
  Latency-insensitive design and central repetitive scheduling. 175-183
  
• Bart D. Theelen, Marc Geilen, Twan Basten, Jeroen Voeten, Stefan Valentin Gheorghita, Sander Stuijk:
  A scenario-aware data flow model for combined long-run average and worst-case performance analysis. 185-194
  

Poster Presentations: Abstracts

• Masahiro Fujita, Subash Shankar, S. Shunsuke:
  Equivalence checking: a rule-based approach. 197
  
• Ansuman Banerjee, Pallab Dasgupta, P. P. Chakrabarti:
  Formal methods for checking realizability of coalitions in 3-party systems. 198
  
• Qi Zhu, Abhijit Davare, Alberto L. Sangiovanni-Vincentelli:
  A semantic-driven synthesis flow for platform-based design. 199
  
• Iñigo Ugarte, Pablo Sanchez:
  Assertion checking of control dominated systems with nonlinear solvers. 200
  
• Frederic Doucet, Ingolf Krüger, Rajesh K. Gupta, R. K. Shyamasundar:
  Compositional interaction specifications for SystemC. 201
  
• Olivier Tardieu, Stephen A. Edwards:
  R-SHIM: deterministic concurrency with recursion and shared variables. 202
  

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