16. LATS 2015: Puerto Vallarta, Mexico

Session 1: Fault Modelling and Simulation

Session 2: Automatic Test Generation

Session 3: Analog Mixed Signal Test

Session 4: Design for Testability

Session 5: Memory: Testing and Fault Injection

Session 6: System-on-Chip Test

Poster Session

Special Session: Issues in Electronic Design Automation: Tolerance Analysis and Design Verification

Session 7: Software-Based Fault Tolerance

Session 8: Built-In Self-Test

Session 9: Issues in EMC, EMI and Radiation

Session 10: Design Verification and Validation

Session 11: Fault Tolerance Architectures

maintained by Schloss Dagstuhl LZI at University of Trier