4. IWSOC 2004: Banff, Alberta, Canada

• Message from the Chairs.
  
• Program Committee.
  

Plenary Session

• Russell Klein:
  SoC Integration Challenges. 3
  

Tutorial 1

• James Paris:
  Integrating a Single Physical Verification Tool for Systems-on-Chip Designs. 7
  
• Vishy Lakshmanan:
  Automated Fixing of Complex/Process Critical DRC Violations in Place and Route Systems Using Calibre in the Synopsys/Milkyway Environment. 7
  

Tutorial 2

• Krzysztof Iniewski, Shahriar Mirabbasi:
  High-Speed I/Os and PLLs for Data Communication Applications. 11-12
  

Tutorial 3

• Ashraf Salem:
  Formal Verification of Digital Circuits. 15
  
• Brian Marshall:
  Beyond P-Cell and Gate-Level: Accuracy Requirements for Simulation of Nanometer SoC Designs. 23-26
  

Sensor IP-Blocks

• Minghua Shi, Amine Bermak, Sofiane Brahim-Belhouari:
  A Real-time Architecture of SOC Selective Gas Sensor Array Using KNN Based on the Dynamic Slope and the Steady State Response. 29-32
  
• Yat-Fong Yung, Amine Bermak:
  A Digital CMOS Imager with Pixel Level Analog-to-digital Converter and Reconfigurable SRAM/Counter. 33-36
  

Modeling and Simulation I

• Alexandre Chureau, Yvon Savaria, El Mostapha Aboulhamid:
  Interface-based Design of Systems-on-Chip using UML-RT. 39-44
  
• Luc Charest, El Mostapha Aboulhamid, Guy Bois:
  Using Design Patterns for Type Unification and Introspection in SystemC. 45-50
  
• L.-P. Lafrance, Yvon Savaria:
  A Framework for Implementing Reusable Digital Signal Processing Modules. 51-54
  
• Samy Meftali, Jean-Luc Dekeyser:
  An Optimal Charge Balancing Model for Fast Distributed SystemC Simulation in IP/SoC Design. 55-58
  

Advanced Arithmetic IP-Blocks

• Wenjing Zhang, Graham A. Jullien, Vassil S. Dimitrov:
  A Programmable Base MDLNS MAC with Self-Generated Look-Up Table. 61-64
  
• Kuo-Hsing Cheng, Shun-Wen Cheng, Chan-Wei Huang:
  64-bit Hybrid Dual-Threshold Voltage Power-Aware Conditional Carry Adder Design. 65-68
  
• Attif A. Ibrahem, Hamed Elsimary, Aly E. Salama:
  FPGA Implementation of Fast Radix 4 Division Algorithm. 69-72
  
• Wei Wang, M. N. S. Swamy, M. Omair Ahmad:
  RNS Application for Digital Image Processing. 77-80
  

Verification and Testing

• Bijan Alizadeh, Zainalabedin Navabi:
  Using Integer Equations to Check PSL Properties in RT Level Design. 83-86
  
• S. Regimbal, Yvon Savaria, Guy Bois:
  Verification Strategy Determination Using Dependence Analysis of Transaction-Level Models. 87-92
  

Analog and Mixed Signal I

• D. Morin, F. Normandin, M.-E. Grandmaison, H. Dang, Yvon Savaria, Mohamad Sawan:
  An Intellectual Property Module for Auto-Calibration of Time-Interleaved Pipelined Analog-to-Digital Converters. 111-114
  
• Hung Tien Bui, Yvon Savaria:
  10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS. 115-118
  
• Robert Chebli, Mohamad Sawan:
  A CMOS High-Voltage DC-DC Up Converter Dedicated for Ultrasonic Applications. 119-122
  
• Masud H. Chowdhury, Yehea I. Ismail:
  Possible Noise Failure Modes in Static and Dynamic Circuits. 123-126
  
• Donghoon Han, Abhijit Chatterjee:
  Simulation-in-the-Loop Analog Circuit Sizing Method using Adaptive Model-based Simulated Annealing. 127-130
  
• Y. Ibrahim, Graham A. Jullien, William C. Miller:
  Ultra Low Noise Signed Digit Arithmetic using Cellular Neural Networks. 136-142
  
• Deng Lei, Wen Gao, Ming-Zeng Hu, Zhenzhou Ji:
  An Efficient VLSI Implementation of MC Interpolation for MPEG-4. 149-152
  
• Ling-zhi Liu, Lin Qiu, Meng-tian Rong, Jiang Li:
  A 2-D Forward/Inverse Integer Transform Processor of H.264 Based on Highly-parallel Architecture. 158-161
  
• Victor H. S. Ha, Sung Kyu Choi, Jong-Gu Jeon, Geon Hyoung Lee, Won-Kap Jang, Woo-Sung Shim:
  Real-time Audio/Video Decoders for Digital Multimedia Broadcasting. 162-167
  
• Hongkyu Kim, D. Scott Wills, Linda M. Wills:
  Empirical Analysis of Operand Usage and Transport in Multimedia Applications. 168-171
  
• Yung-Chi Chang, Chih-Wei Hsu, Liang-Gee Chen:
  MPEG-4 FGS Encoder Design for an Interactive Content-aware MPEG-4 Video Streaming SOC. 172-175
  

Logic Synthesis

• Sherif G. Aly, Ashraf M. Salem:
  Observability-Based RTL Simulation using JAVA. 179-182
  
• Jean-Pierre David, Etienne Bergeron:
  A Step towards Intelligent Translation from High-Level Design to RTL. 183-188
  
• M. Watheq El-Kharashi, M. H. El-Malaki, S. Hammad, Ashraf Salem, Abdel-Moneim Wahdan:
  Towards Automating Hardware/Software Co-Design. 189-192
  
• Ashwin K. Kumaraswamy, Ahmet T. Erdogan, Indrajit Atluri:
  Development of Timing Driven IP Design Flow based on Physical Knowledge Synthesis. 193-197
  
• Milan Pastrnak, Peter Poplavko, Peter H. N. de With, Dirk Farin:
  Data-flow Timing Models of Dynamic Multimedia Applications for Multiprocessor Systems. 206-209
  
• Krzysztof Iniewski, Valery Axelrad, Andrei Shibkov, Artur Balasinski, Marek Syrzycki:
  Design Strategies for ESD Protection in SOC. 210-214
  
• Mikael Olausson, Anders Edman, Dake Liu:
  Bit Memory Instructions for a General CPU. 215-218
  
• Keh-Jeng Chang:
  Accurate On-Chip Variation Modeling to Achieve Design for Manufacturability. 219-222
  

Analog and Mixed Signal II

• K. Ola Andersson, Mark Vesterbacka:
  A Parameterized Cell-Based Design Approach for Digital-to-Analog Converters. 225-228
  
• Erik Sall, Mark Vesterbacka:
  Design of a Comparator in CMOS SOI. 229-232
  
• Iman Y. Taha, Majid Ahmadi, William C. Miller:
  A Sigma-Delta Modulator for Digital Hearing Instruments Using 0.18µm CMOS Technology. 233-236
  
• Sherif Hammouda, Mohamed Dessouky, Mohamed Tawfik, Wael M. Badawy:
  A Fully Automated Approach for Analog Circuit Reuse. 237-240
  

OnChip Bus and Interconnect

• Mountassar Maamoun, Boualem Laichi, Abdelhalim Benbelkacem, Daoud Berkani:
  Interfacing in Microprocessor-based Systems with an Advanced Physical Addressing. 243-246
  
• Krzysztof Iniewski, R. Badalone, M. Lapointe, Marek Syrzycki:
  SERDES Technology for Gigabit I/O Communications in Storage Area Networking. 247-252
  
• Tina Lindkvist, Jacob Löfvenberg, Henrik Ohlsson, Kenny Johansson, Lars Wanhammar:
  A Power-Efficient, Low-Complexity, Memoryless Coding Scheme for Buses with Dominating Inter-Wire Capacitances. 257-262
  
• Daniel Wiklund, Sumant Sathe, Dake Liu:
  Network on Chip Simulations for Benchmarking. 269-274
  
• Jacob Löfvenberg:
  Non-Redundant Coding for Deep Sub-Micron Address Buses. 275-279
  
• Azeddien M. Sllame:
  A Model for a Reusable System-on-a-Chip Hardware Component Integrated with Design Exploration Methodology. 287-290
  
• Xizhi Li, Tiecai Li:
  ECOMIPS: An Economic MIPS CPU Design on FPGA. 291-294
  
• S. A. Rahim, Laurence E. Turner:
  A Field Programmable Bit-Serial Digital Signal Processor. 295-298
  
• Pascal Nsame, Yvon Savaria:
  A Customizable Embedded SoC Platform Architecture. 299-304
  

SoC for Network and Communication Applications

• Holly Pekau, Joshua K. Nakaska, Jim Kulyk, Grant McGibney, James W. Haslett:
  SOC Design of an IF Subsampling Terminal for a Gigabit Wireless LAN with Asymmetric Equalization. 307-313
  
• Richard F. Hobson, Allan R. Dyck, Keith L. Cheung:
  SoC Features for a Multi-Processor WCDMA Base-station Modem. 318-321
  

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