ITC 2011: Anaheim, CA, USA

• Bram Kruseman, Bratislav Tasic, Camelia Hora, Jos Dohmen, Hamidreza Hashempour, Maikel van Beurden, Yizi Xing:
  Defect Oriented Testing for analog/mixed-signal devices. 1-10
  
• Rajesh Mittal, Lakshmanan Balasubramanian, Adesh Sontakke, Harikrishna Parthasarathy, Prakash Narayanan, Puneet Sabbarwal, Rubin A. Parekhji:
  DFT for extremely low cost test of mixed signal SOCs with integrated RF and power management. 1-10
  
• Hsiu-Ming Chang, Kwang-Ting Cheng, Wangyang Zhang, Xin Li, Kenneth M. Butler:
  Test cost reduction through performance prediction using virtual probe. 1-9
  
• Abdullah Mumtaz, Michael E. Imhof, Hans-Joachim Wunderlich:
  P-PET: Partial pseudo-exhaustive test for high defect coverage. 1-8
  
• Tomokazu Yoneda, Keigo Hori, Michiko Inoue, Hideo Fujiwara:
  Faster-than-at-speed test for increased test quality and in-field reliability. 1-9
  
• Yi-Tsung Lin, Jiun-Lang Huang, Xiaoqing Wen:
  Clock-gating-aware low launch WSA test pattern generation for at-speed scan testing. 1-7
  
• Dhruva Acharyya, Kosuke Miyao, David Ting, Daniel Lam, Robert Smith, Pete Fitzpatrick, Brian Buras, John Williamson:
  Architecture and implementation of a truly parallel ATE capable of measuring pico ampere level current. 1-10
  
• Jose Moreira:
  Development of an ATE test cell for at-speed characterization and production testing. 1-10
  
• Yasuhiro Takahashi, Akinori Maeda, Mitsuhiro Ogura:
  Actual implementation of multi domain test: Further reduction of cost of test. 1-8
  
• Guihai Yan, Xiaowei Li:
  Online timing variation tolerance for digital integrated circuits. 1-10
  
• Wing Chiu Tam, R. D. (Shawn) Blanton:
  Physically-aware analysis of systematic defects in integrated circuits. 1-10
  
• Urban Ingelsson, Bashir M. Al-Hashimi:
  Investigation into voltage and process variation-aware manufacturing test. 1-10
  
• Zhaobo Zhang, Krishnendu Chakrabarty, Zhanglei Wang, Zhiyuan Wang, Xinli Gu:
  Smart diagnosis: Efficient board-level diagnosis and repair using artificial neural networks. 1-9
  
• Kenneth P. Parker, Shuichi Kameyama, David Dubberke:
  Surviving state disruptions caused by test: A case study. 1-8
  
• Heiko Ehrenberg, Bob Russell:
  IEEE Std 1581 - A standardized test access methodology for memory devices. 1-9
  
• Ivo Koren, Ben Schuffenhauer, Frank Demmerle, Frank Neugebauer, Gert Pfahl, Dirk Rautmann:
  Multi-site test of RF transceivers on low-cost digital ATE. 1-10
  
• Dragoljub Gagi Drmanac, Michael Laisne:
  Wafer probe test cost reduction of an RF/A device by automatic testset minimization - A case study. 1-10
  
• Aritra Banerjee, Shreyas Sen, Shyam Kumar Devarakond, Abhijit Chatterjee:
  Accurate signature driven power conscious tuning of RF systems using hierarchical performance models. 1-9
  
• Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy:
  Low power compression utilizing clock-gating. 1-8
  
• Yiwen Shi, Kantapon Kaewtip, Wan-Chan Hu, Jennifer Dworak:
  Partial state monitoring for fault detection estimation. 1-10
  
• Enamul Amyeen, Andal Jayalakshmi, Srikanth Venkataraman, Sundar V. Pathy, Ewe C. Tan:
  Logic BIST silicon debug and volume diagnosis methodology. 1-10
  
• A. J. van de Goor, Said Hamdioui, Halil Kukner:
  Generic, orthogonal and low-cost March Element based memory BIST. 1-10
  
• Renan Alves Fonseca, Luigi Dilillo, Alberto Bosio, Patrick Girard, Serge Pravossoudovitch, Arnaud Virazel, Nabil Badereddine:
  On using address scrambling to implement defect tolerance in SRAMs. 1-8
  
• Yi-Chung Chang, Shi-Yu Huang, Chao-Wen Tzeng, Jack T. Yao:
  A fully cell-based design for timing measurement of memory. 1-10
  
• Friedrich Hapke, Jürgen Schlöffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, M. Reese, J. Rearick, Jason Rivers:
  Cell-aware analysis for small-delay effects and production test results from different fault models. 1-8
  
• Priyamvada Vijayakumar, Vikram B. Suresh, Sandip Kundu:
  Lithography aware critical area estimation and yield analysis. 1-8
  
• Anne E. Gattiker, Phil Nigh:
  Using well/substrate bias manipulation to enhance voltage-test-based defect detection. 1-6
  
• George Theodorou, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos:
  A Software-Based Self-Test methodology for on-line testing of processor caches. 1-10
  
• Kuo-An Chen, Tsung-Wei Chang, Meng-Chen Wu, Mango Chia-Tso Chao, Jing-Yang Jou, Sonair Chen:
  Design-for-debug layout adjustment for FIB probing and circuit editing. 1-9
  
• Saeed Shamshiri, Amirali Ghofrani, Kwang-Ting Cheng:
  End-to-end error correction and online diagnosis for on-chip networks. 1-10
  
• Kanad Basu, Prabhat Mishra, Priyadarsan Patra:
  Efficient combination of trace and scan signals for post silicon validation and debug. 1-8
  
• Mitchell Lin, Tyler Tolman:
  Analyzing ATE interconnect performance for serial links of 10 Gbps and above. 1-8
  
• Hideo Okawara:
  Elegant construction of SSC implemented signal by AWG and organized under-sampling of wideband signal. 1-8
  
• Masahiro Ishida, Kiyotaka Ichiyama, Daisuke Watanabe, Masayuki Kawabata, Toshiyuki Okayasu:
  Real-time testing method for 16 Gbps 4-PAM signal interface. 1-10
  
• A. M. Majid, David C. Keezer:
  Multi-function multi-GHz ATE extension using state-of-the-art FPGAs. 1-10
  
• Yuta Yamato, Xiaoqing Wen, Michael A. Kochte, Kohei Miyase, Seiji Kajihara, Laung-Terng Wang:
  A novel scan segmentation design method for avoiding shift timing failure in scan testing. 1-8
  
• Jen-Yang Wen, Yu-Chuan Huang, Min-Hong Tsai, Kuan-Yu Liao, James Chien-Mo Li, Ming-Tung Chang, Min-Hsiu Tsai, Chih-Mou Tseng, Hung-Chun Li:
  Test clock domain optimization for peak power supply noise reduction during scan. 1-8
  
• Swapnil Bahl, Roberto Mattiuzzo, Shray Khullar, Akhil Garg, S. Graniello, Khader S. Abdel-Hafez, Salvatore Talluto:
  State of the art low capture power methodology. 1-10
  
• Stephen K. Sunter, Aubin Roy:
  Adaptive parametric BIST of high-speed parallel I/Os via standard boundary scan. 1-9
  
• Pankaj Pant, Eric Skeels:
  Hardware hooks for transition scan characterization. 1-8
  
• Liang-Chi Chen, Peter Dahlgren, Paul Dickinson, Scott Davidson:
  Transition test bring-up and diagnosis on UltraSPARC^TM processors. 1-10
  
• Dilip K. Bhavsar, Steve Poehlman:
  Test access and the testability features of the Poulson multi-core Intel Itanium® processor. 1-8
  
• Sreejit Chakravarty, Binh Dang, Darcy Escovedo, A. J. Haas:
  Optimal manufacturing flow to determine minumum operating voltage. 1-10
  
• Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski:
  EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. 1-9
  
• Manish Sharma, Avijit Dutta, Wu-Tung Cheng, Brady Benware, Mark Kassab:
  A novel Test Access Mechanism for failure diagnosis of multiple isolated identical cores. 1-9
  
• V. R. Devanathan, Srinivas Kumar Vooka:
  Techniques to improve memory interface test quality for complex SoCs. 1-10
  
• Kapil R. Gotkhindikar, W. Robert Daasch, Kenneth M. Butler, John M. Carulli Jr., Amit Nahar:
  Die-level adaptive test: Real-time test reordering and elimination. 1-10
  
• Nik Sumikawa, Dragoljub Gagi Drmanac, Li-C. Wang, LeRoy Winemberg, Magdy S. Abadir:
  Forward prediction based on wafer sort data - A case study. 1-10
  
• Andras Kun, Ralf Arnold, Peter Heinrich, Gwenolé Maugard, Huaxing Tang, Wu-Tung Cheng:
  Deterministic IDDQ diagnosis using a net activation based model. 1-10
  
• Siva Sudani, Minshun Wu, Degang Chen:
  A novel robust and accurate spectral testing method for non-coherent sampling. 1-10
  
• Takahiro J. Yamaguchi, Mani Soma, Takafumi Aoki, Yasuo Furukawa, Katsuhiko Degawa, Kunihiro Asada, Mohamed Abbas, Satoshi Komatsu:
  Application of a continuous-time level crossing quantization method for timing noise measurements. 1-10
  
• Ender Yilmaz, Sule Ozev, Kenneth M. Butler:
  Adaptive multidimensional outlier analysis for analog and mixed signal circuits. 1-8
  
• Brandon Noia, Krishnendu Chakrabarty:
  Pre-bond probing of TSVs in 3D stacked ICs. 1-10
  
• Ken Smith, Peter Hanaway, Mike Jolley, Reed Gleason, Eric Strid, Tom Daenen, Luc Dupas, Bruno Knuts, Erik Jan Marinissen, Marc Van Dievel:
  Evaluation of TSV and micro-bump probing for wide I/O testing. 1-10
  
• Chun-Chuan Chi, Erik Jan Marinissen, Sandeep Kumar Goel, Cheng-Wen Wu:
  Post-bond testing of 2.5D-SICs and 3D-SICs containing a passive silicon interposer base. 1-10
  
• Bill Dally:
  Power, programmability, and granularity: The challenges of ExaScale computing. 12
  
• Jyuo-Min Shyu:
  A systems perspective on the R&D of industrial technology. 13
  
• Phil Nigh:
  Industry leaders panel - How will testing change in the next 10 years? 1
  
• Jing Zeng:
  Challenges and best practices in advanced silicon debug. 1
  
• Bailarico Balangue:
  In circuit test (ICT): The king is dead; long live the king! 1
  
• Xinli Gu:
  The gap: Test challenges in Asia manufacturing field. 1
  

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